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GALS,Design och simulering för FPGA med VHDL / GALS,Design and simulation for FPGA with VHDL

<p>Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced. </p><p>GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload. </p><p>Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.</p>

Identiferoai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-2644
Date January 2004
CreatorsEk, Tobias
PublisherLinköping University, Department of Electrical Engineering, Institutionen för systemteknik
Source SetsDiVA Archive at Upsalla University
LanguageSwedish
Detected LanguageEnglish
TypeStudent thesis, text
RelationLiTH-ISY-Ex-ET, ; 3568

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