Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction.
This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts:
The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications.
To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications.
To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs.
The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET.
The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits.
This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts:
The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening.
The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/116216 |
| Date | 05 September 2023 |
| Creators | Zhang, Ruizhe |
| Contributors | Electrical Engineering, Zhang, Yuhao, Orlowski, Mariusz Kriysztof, Li, Qiang, Dimarino, Christina Marie, Asryan, Levon Volodya |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Dissertation |
| Format | ETD, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
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