The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice due to its low cost and ability to be deposited via DC reactive sputtering. In the absence of an acceptable ZTO wet etch process, a plasma-etching process using Ar/CH₄ is developed for both 1:1 and 2:1 ZTO compositions. An Ar/CH₄ plasma etch process is also designed for indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and indium tin oxide (ITO). Ar/CH₄ dry etches have excellent selectivity with respect to SiO₂, providing a route for obtaining patterned ZTO channels. A critical asset of ZTO process integration involves removing polymer deposits after ZTO etching without active layer damage.
A ZTO process is developed for the fabrication of integrated circuits which use ZTO channel enhancement-mode TFTs. Such ZTO TFTs exhibit incremental and average mobilities of 23 and 18 cm²V⁻¹s⁻¹, respectively, turn-on voltages approximately 0 to 1.5 V and subthreshold swings below 0.5 V/dec when annealed in air at 400 °C for 1 hour. Several types of ZTO TFT circuits are realized for the first time. Despite large parasitic capacitances due to large gate-source and gate-drain overlaps, AC/DC rectifiers are fabricated and found to operate in the MHz range. Thus, they are usable for RFID and other equivalent-speed applications. Finally, a ZTO process for simultaneously fabricating both enhancement-mode and depletion-mode TFTs on a single substrate using a single target and anneal step is developed. This dual-channel process is used to build a high-gain two-transistor enhancement/depletion inverter. At a rail voltage of 10 V, this inverter has a gain of 10.6 V/V, the highest yet reported for an AOS-based inverter. This E/D inverter is an important new functional block which will enable the realization of more complex digital logic circuits. / Graduation date: 2009
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/9975 |
| Date | 23 December 2008 |
| Creators | Heineck, Daniel Philip |
| Contributors | Wager, John |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
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