Instruction Timing Analysis for Linux/x86-based Embedded and Desktop Systems

Description

Real-time aspects are becoming more important in
standard desktop PC environments and x86 based
processors are being utilized in embedded systems
more often.
While these processors were not created for use
in hard real time systems, they are fast and
inexpensive and can be used if it is possible
to determine the worst case execution time.

Information on CPU caches (L1, L2) and
branch prediction architecture is necessary
to simulate best and worst cases in execution
timing, but is often not detailed
enough and sometimes not published at all.

This document describes how the underlying
hardware can be analysed to obtain
this information.

Links & Downloads

1. urn:nbn:de:swb:ch1-200501401
2. https://monarch.qucosa.de/id/qucosa%3A18389
3. https://monarch.qucosa.de/api/qucosa%3A18389/attachment/ATT-0/
4. https://monarch.qucosa.de/api/qucosa%3A18389/attachment/ATT-1/
5. https://monarch.qucosa.de/api/qucosa%3A18389/attachment/ATT-2/
6. https://monarch.qucosa.de/api/qucosa%3A18389/attachment/ATT-3/

Tags

branch prediction

cache architecture

info:eu-repo/classification/ddc/004

ddc:004

Analyse

Benchmark

Cache-Speicher

LINUX

Timing

Additional Fields

Identifer	oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:18389
Date	19 October 2005
Creators	John, Tobias
Contributors	Baumgartl, Robert, Protzel, Peter, Technische Universität Chemnitz
Source Sets	Hochschulschriftenserver (HSSS) der SLUB Dresden
Language	English
Detected Language	English
Type	info:eu-repo/semantics/publishedVersion, doc-type:masterThesis, info:eu-repo/semantics/masterThesis, doc-type:Text
Rights	info:eu-repo/semantics/openAccess