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Teaching In-Memory Database Systems the Detection of Hardware Errors

The key objective of database systems is to reliably manage data, whereby high query throughput and low query latency are core requirements. To satisfy these requirements, database systems constantly adapt to novel hardware features. Although it has been intensively studied and commonly accepted that hardware error rates in terms of bit flips increase dramatically with the decrease of the underlying chip structures, most database system research activities neglected this fact, leaving error (bit flip) detection as well as correction to the underlying hardware. Especially for main memory, silent data corruption (SDC) as a result of transient bit flips leading to faulty data is mainly detected and corrected at the DRAM and memory-controller layer. However, since future hardware becomes less reliable and error detection as well as correction by hardware becomes more expensive, this free ride will come to an end in the near future. To further provide a reliable data management, an emerging research direction is employing specific and tailored protection techniques at the database system level. Following that, we are currently developing and implementing an adopted system design for state-of-the-art in-memory column stores. In our lightning talk, we will summarize our current state and outline future work.

Identiferoai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:82178
Date18 January 2023
CreatorsLehner, Wolfgang, Habich, Dirk, Kolditz, Till
PublisherIEEE
Source SetsHochschulschriftenserver (HSSS) der SLUB Dresden
LanguageEnglish
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/acceptedVersion, doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text
Rightsinfo:eu-repo/semantics/openAccess
Relation978-1-5386-5520-7, 10.1109/ICDE.2018.00203, info:eu-repo/grantAgreement/Deutsche Forschungsgemeinschaft/Exzellenzcluster/194636624//EXC 1056: Zentrum für Perspektiven in der Elektronik Dresden

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