Nowadays, implementing a complex system, which executes various applications with different levels of assurance, is a growing trend in modern embedded real-time systems to meet cost, timing, and power consumption requirements. Medical devices, automotive, and avionics industries are the most common safety-critical applications, exploiting these systems known as Mixed-Criticality (MC) systems. MC applications are real-time, and to ensure the correctness of these applications, it is essential to meet strict timing requirements as well as functional specifications. The correct design of such MC systems requires a thorough understanding of the system's functions and their importance to the system. A failure/deadline miss in functions with various criticality levels has a different impact on the system, from no effect to catastrophic consequences. Failure in the execution of tasks with higher criticality levels (HC tasks) may lead to system failure and cause irreparable damage to the system, while although Low-Criticality (LC) tasks assist the system in carrying out its mission successfully, their failure has less impact on the system's functionality and does not harm the system itself to fail.
In order to guarantee the MC system safety, tasks are analyzed with different assumptions to obtain different Worst-Case Execution Times (WCETs) corresponding to the multiple criticality levels and the operation mode of the system. If the execution time of at least one HC task exceeds its low WCET, the system switches from low-criticality mode (LO mode) to high-criticality mode (HI mode). Then, all HC tasks continue executing by considering the high WCET to guarantee the system's safety. In this HI mode, all or some LC tasks are dropped/degraded in favor of HC tasks to ensure HC tasks' correct execution.
Determining an appropriate low WCET for each HC task is crucial in designing efficient MC systems and ensuring QoS maximization. However, in the case where the low WCETs are set correctly, it is not recommended to drop/degrade the LC tasks in the HI mode due to its negative impact on the other functions or on the entire system in accomplishing its mission correctly. Therefore, how to analyze the task dropping in the HI mode is a significant challenge in designing efficient MC systems that must be considered to guarantee the successful execution of all HC tasks to prevent catastrophic damages while improving the QoS.
Due to the continuous rise in computational demand for MC tasks in safety-critical applications, like controlling autonomous driving, the designers are motivated to deploy MC applications on multi-core platforms. Although the parallel execution feature of multi-core platforms helps to improve QoS and ensures the real-timeliness, high power consumption and temperature of cores may make the system more susceptible to failures and instability, which is not desirable in MC applications. Therefore, improving the QoS while managing the power consumption and guaranteeing real-time constraints is the critical issue in designing such MC systems in multi-core platforms.
This thesis addresses the challenges associated with efficient MC system design. We first focus on application analysis by determining the appropriate WCET by proposing a novel approach to provide a reasonable trade-off between the number of scheduled LC tasks at design-time and the probability of mode switching at run-time to improve the system utilization and QoS. The approach presents an analytic-based scheme to obtain low WCETs based on the Chebyshev theorem at design-time. We also show the relationship between the low WCETs and mode switching probability, and formulate and solve the problem for improving resource utilization and reducing the mode switching probability. Further, we analyze the LC task dropping in the HI mode to improve QoS. We first propose a heuristic in which a new metric is defined that determines the number of allowable drops in the HI mode. Then, the task schedulability analysis is developed based on the new metric. Since the occurrence of the worst-case scenario at run-time is a rare event, a learning-based drop-aware task scheduling mechanism is then proposed, which carefully monitors the alterations in the behavior of MC systems at run-time to exploit the dynamic slacks for improving the QoS.
Another critical design challenge is how to improve QoS using the parallel feature of multi-core platforms while managing the power consumption and temperature of these platforms. We develop a tree of possible task mapping and scheduling at design-time to cover all possible scenarios of task overrunning and reduce the LC task drop rate in the HI mode while managing the power and temperature in each scenario of task scheduling. Since the dynamic slack is generated due to the early execution of tasks at run-time, we propose an online approach to reduce the power consumption and maximum temperature by using low-power techniques like DVFS and task re-mapping, while preserving the QoS. Specifically, our approach examines multiple tasks ahead to determine the most appropriate task for the slack assignment that has the most significant effect on power consumption and temperature. However, changing the frequency and selecting a proper task for slack assignment and a suitable core for task re-mapping at run-time can be time-consuming and may cause deadline violation. Therefore, we analyze and optimize the run-time scheduler.:1. Introduction
1.1. Mixed-Criticality Application Design
1.2. Mixed-Criticality Hardware Design
1.3. Certain Challenges and Questions
1.4. Thesis Key Contributions
1.4.1. Application Analysis and Modeling
1.4.2. Multi-Core Mixed-Criticality System Design
1.5. Thesis Overview
2. Preliminaries and Literature Reviews
2.1. Preliminaries
2.1.1. Mixed-Criticality Systems
2.1.2. Fault-Tolerance, Fault Model and Safety Requirements
2.1.3. Hardware Architectural Modeling
2.1.4. Low-Power Techniques and Power Consumption Model
2.2. Related Works
2.2.1. Mixed-Criticality Task Scheduling Mechanisms
2.2.2. QoS Improvement Methods in Mixed-Criticality Systems
2.2.3. QoS-Aware Power and Thermal Management in Multi-Core Mixed-Criticality Systems
2.3. Conclusion
3. Bounding Time in Mixed-Criticality Systems
3.1. BOT-MICS: A Design-Time WCET Adjustment Approach
3.1.1. Motivational Example
3.1.2. BOT-MICS in Detail
3.1.3. Evaluation
3.2. A Run-Time WCET Adjustment Approach
3.2.1. Motivational Example
3.2.2. ADAPTIVE in Detail
3.2.3. Evaluation
3.3. Conclusion
4. Safety- and Task-Drop-Aware Mixed-Criticality Task Scheduling
4.1. Problem Objectives and Motivational Example
4.2. FANTOM in detail
4.2.1. Safety Quantification
4.2.2. MC Tasks Utilization Bounds Definition
4.2.3. Scheduling Analysis
4.2.4. System Upper Bound Utilization
4.2.5. A General Design Time Scheduling Algorithm
4.3. Evaluation
4.3.1. Evaluation with Real-Life Benchmarks
4.3.2. Evaluation with Synthetic Task Sets
4.4. Conclusion
5. Learning-Based Drop-Aware Mixed-Criticality Task Scheduling
5.1. Motivational Example and Problem Statement
5.2. Proposed Method in Detail
5.2.1. An Overview of the Design-Time Approach
5.2.2. Run-Time Approach: Employment of SOLID
5.2.3. LIQUID Approach
5.3. Evaluation
5.3.1. Evaluation with Real-Life Benchmarks
5.3.2. Evaluation with Synthetic Task Sets
5.3.3. Investigating the Timing and Memory Overheads of ML Technique
5.4. Conclusion
6. Fault-Tolerance and Power-Aware Multi-Core Mixed-Criticality System Design
6.1. Problem Objectives and Motivational Example
6.2. Design Methodology
6.3. Tree Generation and Fault-Tolerant Scheduling and Mapping
6.3.1. Making Scheduling Tree
6.3.2. Mapping and Scheduling
6.3.3. Time Complexity Analysis
6.3.4. Memory Space Analysis
6.4. Evaluation
6.4.1. Experimental Setup
6.4.2. Analyzing the Tree Construction Time
6.4.3. Analyzing the Run-Time Timing Overhead
6.4.4. Peak Power Management and Thermal Distribution for Real-Life and Synthetic Applications
6.4.5. Analyzing the QoS of LC Tasks
6.4.6. Analyzing the Peak Power Consumption and Maximum Temperature
6.4.7. Effect of Varying Different Parameters on Acceptance Ratio
6.4.8. Investigating Different Approaches at Run-Time
6.5. Conclusion
7. QoS- and Power-Aware Run-Time Scheduler for Multi-Core Mixed-Criticality Systems
7.1. Research Questions, Objectives and Motivational Example
7.2. Design-Time Approach
7.3. Run-Time Mixed-Criticality Scheduler
7.3.1. Selecting the Appropriate Task to Assign Slack
7.3.2. Re-Mapping Technique
7.3.3. Run-Time Management Algorithm
7.3.4. DVFS governor in Clustered Multi-Core Platforms
7.4. Run-Time Scheduler Algorithm Optimization
7.5. Evaluation
7.5.1. Experimental Setup
7.5.2. Analyzing the Relevance Between a Core Temperature and Energy Consumption
7.5.3. The Effect of Varying Parameters of Cost Functions
7.5.4. The Optimum Number of Tasks to Look-Ahead and the Effect of Task Re-mapping
7.5.5. The Analysis of Scheduler Timings Overhead on Different Real Platforms
7.5.6. The Latency of Changing Frequency in Real Platform
7.5.7. The Effect of Latency on System Schedulability
7.5.8. The Analysis of the Proposed Method on Peak Power, Energy and Maximum Temperature Improvement
7.5.9. The Analysis of the Proposed Method on Peak power, Energy and Maximum Temperature Improvement in a Multi-Core Platform Based on the ODROID-XU3 Architecture
7.5.10. Evaluation of Running Real MC Task Graph Model (Unmanned Air Vehicle) on Real Platform
7.6. Conclusion
8. Conclusion and Future Work
8.1. Conclusions
8.2. Future Work
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:82567 |
| Date | 06 December 2022 |
| Creators | Ranjbar, Behnaz |
| Contributors | Kumar, Akash, Shrivastava, Aviral, Technische Universität Dresden, Sharif University of Technology, Behnaz Ranjbar |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 10.1109/DSD.2019.00084, 10.1109/ACCESS.2020.3031039, 10.1109/TCAD.2020.3033374, 10.23919/DATE51398.2021.9474263, 10.1109/TCAD.2021.3082495, 10.1109/TCAD.2021.3127867, 10.3390/computers11070101 |
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