LEDs are being developed as the next generation lighting source due to their high
efficiency and long life time, with a potential to save $15 billion per year in energy cost
by 2020. State of the art LEDs are capable of emitting light at ~115 lm/W and have
lifetime over 50,000 hours. It has already surpassed the efficiency of incandescent light
sources, and is even comparable to that of fluorescent lamps. Since the total luminous
flux generated by a single LED is considerably lower than other light sources, to be
competitive the total light output must be increased with higher forward currents and
packages of multiple LEDs. However, both of these solutions would increase the
junction temperature, which degrades the performance of the LED--as the operating
temperature goes up, the light intensity decreases, the lifetime is reduced, and the light
color changes. The word "junction" refers to the p-n junction within the LED-chips.
Critical to the temperature rise in high powered LED sources is the very large heat flux at
the die level (100-500 W/cm2) which must be addressed in order to lower the operating
temperature in the die. It is possible to address the spreading requirements of high
powered LED die through the use of power electronic substrates for efficient heat
dissipation, especially when the die are directly mounted to the power substrate in a chipon-
board (COB) architecture. COB is a very attractive technology for packaging power
LEDs which can lead improved price competiveness, package integration and thermal
performance.
In our work high power LED-chips (>1W/die) implementing COB architectures
were designed and studied. Substrates for these packaging configurations include two
types of power electronic substrates; insulated-metal-substrates (IMS) and direct-bonded-copper (DBC). To lower the operating temperature both the thermal impedance of the
dielectric layer and the heat spreading in the copper circuit layers must be studied. In the
analysis of our architectures, several lead free solders and thermal interface materials
were considered. We start with the analysis of single-chip LED package and extend the
result to the multi-chip arrays. The thermal resistance of the system is only a function of
geometry and thermal conductivity if temperature-independent properties are used. Thus
through finite element analysis (ANSYS) the effect of geometry and thermal conductivity
on the thermal resistance was investigated. The drawback of finite element analysis is
that many simulations must be conducted whenever the geometry or the thermal
conductivity is changed. To bypass same of the computational load, a thermal resistance
network was developed. We developed analytical expressions of the thermal resistance,
especially focusing on the heat spreading effect at the substrate level. Finally, multi-chip
LED arrays were analyzed through finite element analysis and an analytical analysis;
where die-spacing is another important factor to determine the junction temperature.
With this thermal analysis, critical design considerations were investigated in order to
minimize device temperatures and thereby maximizing light output while also
maximizing device reliability.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/31803 |
| Date | 17 November 2009 |
| Creators | Ha, Min Seok |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Thesis |
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