Zugl.: Dresden, Techn. Univ., Diss., 2008

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / This paper will present methods to both measure the unmodulated carrier power of a modulated signal and to estimate the unmodulated carrier power level from the measured power spectrum. The unmodulated carrier power level is needed to convert measured spectra into units of dBc.

This Dissertation is a study of Switched Mode Power Supply (SMPS) miniaturization and how to effectively use the available technologies to achieve the ultimate goal of a reduced size without loss of functionality while maintaining a cost effective design. This research investigates several methods used to obtain low loss, highly compact power supplies. Within these constraints, the Dissertation investigates the issues of design, materials, and cost in order to design and achieve these miniaturized power supplies. This research addresses high performance ceramic, passive component integration. Three key issues; electrical characterization, thermal analysis and simulation, and material characterization, are examined in this work. Thick film passive components (capacitors and resistors) on AlN have been developed. Also, guidelines for the design implementation and steps necessary to integrate these passive components on prefired alumina (Al2O3) and aluminum nitride (AlN) ceramic surfaces, for power electronic applications, have been generated. The use of aluminum nitride, as a high performance ceramic substrate and the resulting issues concerning compatible inks, have been investigated. Since a sizable amount of heat is generated by power electronic circuits, the integrated components are analyzed with respect to tolerance and degeneration over a range of temperatures and frequencies. Thick film capacitors on the order of 120pF/mm2 with breakdown voltage ratings of 250V have been developed on prefired AlN. Resistors were developed with impedances ranging from 10W to 10MegW. Thermal measurements, of these resistors, show that the thermal conductivity of the aluminum nitride with passivation layer is two to three times that of alumina. Several versions of a typical SMPS boost circuit have been generated using Direct Bond Copper (DBC) on ceramic, Insulated Metal Substrate (IMS), Printed Circuit Boards (PCB), and prefired ceramic thick film technology. The integrated passive components developed are applied on prefired ceramic versions and compared to the DBC, IMS and PCB versions. A small daughter board consisting of the boost circuit control is introduced to further supplement miniaturization and reduce cost. The daughter board uses thick film technology with integrated thick film resistors. The design of the mother board, which houses the power boost section,can be designedand implemented on virtually any type of substrate (PCB, DBC, IMS, or conventional thick film). The fabrication and testing of each version is reported in this work. / Ph. D.

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No description available.

The non-isolated POL converters are widely used in computers, telecommunication systems, portable electronics, and many other applications. These converters are usually constructed using discrete components, and operated at a lower frequency around 200 ~ 600 kHz to achieve a decent efficiency at the middle of 80's%. The passive components, such as inductors and capacitors, are bulky, and they occupy a considerable foot-print. As the power demands increase for POL converters and the limited real estate of the mother board, the POL converters must be made significantly smaller than what they have demonstrated to date. To achieve these goals, two things have to happen simultaneously. The first is a significant increase in the switching frequency to reduce the size and weight of the inductors and capacitors. The second is to integrate passive components, especially magnetics, with active components to realize the needed power density. Today, this concept has been demonstrated at a level less than 5A and a power density around 300-700W/in3 by using silicon-based power semiconductors. This might address the need of small hand-held equipment such as PDAs and smart phones. However, it is far from meeting the needs for applications, such as netbook, notebook, desk-top and server applications where tens and hundreds of amperes are needed. After 30 years of silicon MOSFET development, the silicon has approached its theoretical limits. The recently emerged GaN transistors as a possible candidate to replace silicon devices in various power conversion applications. GaN devices are high electron mobility transistors (HEMT) and have higher band-gap, higher electron mobility, and higher electron velocity than silicon devices, and offer the potential benefits for high frequency power conversions. By implementing the GaN device, it is possible to build the POL converter that can achieve high frequency, high power density, and high efficiency at the same time. GaN technology is in its early stage; however, its significant gains are projected in the future. The first generation GaN devices can outperform the state-of-the-art silicon devices with superior FOM and packaging. The objective of this work is to explore the design of high frequency, high power density 12 V input POL modules with GaN devices and the 3D integration technique. This work discusses the fundamental differences between the enhancement mode and depletion mode GaN transistors, the effect of parasitics on the performance of the high frequency GaN POL, the 3D technique to integrate the active layer with LTCC magnetic substrate, and the thermal design of a high density module using advanced substrates with improved thermal conductivity. The hardware demonstrators are two 12 V to 1.2 V highly integrated 3D POL modules, the single phase 10 A module and two phase 20 A module, all built with depletion mode GaN transistors and low profile LTCC inductors. / Master of Science

With the potential to improve upon silicon (Si ) based power electronics exhausted, the push for improvement now lies with wide bandgap (WBG) materials like gallium nitride (GaN). With a larger bandgap, higher electron mobility, and higher electrical field strength than Si, GaN high electron mobility transistors (HEMTs) can have lower on-state losses and higher switching frequencies in a smaller package. This makes GaN HEMTs an attractive choice for compact, high efficiency power devices. However, the package designs used for Si cannot be used for GaN HEMTs, requiring novel, chip-scale designs that are optimized for low electrical parasitics and low thermal resistance. Recent Center for Power Electronics (CPES) research culminated in a printed circuit board-direct bonded copper (PCB-DBC) hybrid package to house a 650 V, 150 A GaN HEMT. Called the PCB-Interposer-on-DBC package, it utilizes a DBC for heat extraction while using vertical pin interconnects to minimize electrical parasitics. Previous work did not investigate the design's locations of expected failure or reliability. With thermally generated mechanical fatigue a consistent cause of electronics failure, it must be investigated for the design to move beyond the prototyping phase. Thermo-mechanical fatigue failure is the brittle fracture of bonds caused by thermally induced warpage. The thermal warpage is the consequence of the bonded package components having a coefficient of expansion (CTE) mismatch while being subjected to temperature changes during operation. Multiphysics simulation software have previously quantified the fatigue placed on bonds exposed to these cyclic conditions, with a common metric being the volume-averaged inelastic strain energy density gained per cycle (ΔWavg). ΔWavg can identify which bonds are subjected to the greatest amount of fatigue and will thus fail first, and then quantify the effect of design alterations on those vulnerable bonds. A common design alteration seen in solder ball packaging is adding a polymeric material that encapsulates the bonds. If the polymer has a CTE like that of the package substrates and an elastic modulus (E) exceeding 1 GPa, it constrains the thermal warpage and lowers bond fatigue. This thesis uses thermo-mechanical simulations to provide evidence on which bonds fail first in the package, and that material-based methods of fatigue reduction used in solder ball packing apply to this novel package. Chapter 1 explains how a desire to reduce the cost and increase the performance of electric vehicles led to the development of the PCB-Interposer-on-DBC design, and that the package's response to thermo-mechanical fatigue is unknown. The concepts of thermo-mechanical fatigue and using encapsulants to reduce it are established, along with how simulations are used to study said fatigue. Chapter 2 serves two purposes, the first being an explanation of the simulation settings and metrics used to establish the quality and assumptions used, and the second being a beginners guide on how to create these simulations. Chapter 3 identifies the most probable locations of initial package failure and identifies what encapsulants minimize ΔWavg on those locations. The sintered silver bond expected to fail first is the Internal Gate bond, and an encapsulant with the maximum possible E and 8 ppm/°C minimizes ΔWavg. The Sn60Pb40 bond expected to fail first is the External Source 4 bond and using an encapsulant with the maximum possible E and a CTE of 24 ppm/°C minimizes ΔWavg. While ΔWavg cannot determine which of the two bonds fails first as they are made of different materials, the Internal Gate is prioritized as it has a higher per-cycle fatigue and to prevent loss of the gate signal. Chapter 4 demonstrates how to perform a brief encapsulant study while ranking the expected cycles to failure when using four different encapsulant options. The first two options are to use no encapsulant or silicone gel. As the elastic modulus of silicone gels are too low to restrict or couple the thermally generated warpage, using silicone gel results in a ΔWavg comparable to using no encapsulant. The rigid encapsulant with the properties most like the optimal encapsulant identified for Internal Gate has the lowest ΔWavg¬ of the encapsulants tested. Guidelines are established for what properties an encapsulant must have to outperform said rigid encapsulant. This work uses simulations to provide evidence that encapsulant methods used in ball grid array (BGA) packaging to reduce fatigue apply to a novel GaN HEMT package. By identifying the first-failure locations of the package, establishing what existing encapsulant should be used, and what encapsulation it should eventually be replaced with, these results provide the groundwork for both experimental temperatures cycling and more complex simulations. Such work fills the gap in understanding the reliable lifetime and common failure mechanisms of the PCB-Interposer-on-DBC package. / Master of Science / In modern engineering, the cause of failure in a well-designed electronic device is typically not a single event. Rather, it is the culmination of many smaller events that each cause a minor amount of damage. This cycle of repeated, minor damage is called fatigue. When working with power or IC electronics, the most common type of fatigue occurs due to the device's changing temperature. Electronics undergo continuously changing temperatures due to the environment and their own energy losses, causing repeated cycles of heating and cooling. All materials expand upon heating and contract upon cooling , and the magnitude of this change is the coefficient of thermal expansion (CTE). Electronic devices are comprised of dissimilar materials, so disparate components will expand and contract at different rates. Holding these disparate materials together are bonds, which in the process of holding this warped structure together, also deform. This deformation causes permanent damage, which accumulates in the bonds until they break. As these bonds often serve as pathways for the electrical signal or heat extraction, their failure either degrades or breaks the electrical devices. While preventing bond fatigue is impractical, there are strategies to extend the operating lifetime. A common option used elsewhere is to encase the bonds with a polymer. If the polymer's properties are carefully selected, they can reduce the structural warpage, thereby reducing the fatigue on the bonds. Previous Center for Power Electronics (CPES) research has culminated in a new electronics device called the Printed Circuit Board-Interposer-on-Direct Bonded Copper package (PCB-Interposer-on-DBC package). While general trends suggest which bonds will fail first and what kind of polymers reduce fatigue, this information has not yet been confirmed. This thesis uses computer simulations to identify which bonds will likely fail first, and to provide evidence that existing methods for reducing fatigue are viable for this unique package. The simulations work by subjecting a 3D model to a cycle of heating and cooling, called a temperature cycle, and quantifying the damage sustained by the bonds for every cycle. Chapter 1 describes the relevant details leading to this package design, the importance of thermo-mechanical reliability in the design of electronics, and how to use simulation software to quantify reductions in bond fatigue. Chapter 2 explains how to set up these simulations and evaluate their quality. Chapter 3 identifies the initial locations of package failure and identifies what are the most optimal encapsulants to use. Chapter 4 identifies what existing encapsulant will maximize the package lifetime in experimental temperature cycling.

Made available in DSpace on 2016-08-17T14:52:57Z (GMT). No. of bitstreams: 1 Paulino de Almeida Cantanhede Filho.pdf: 1682767 bytes, checksum: a5fce1801fd45fddf7e98305e0e9b053 (MD5) Previous issue date: 2005-03-14 / Guidelines for evaluation and selection of COTS (Commercial-Off-The-Shelf) products. Comes a methodology for the Development based on COTS (DBC) in the Requirements Engineering, being approached the evaluation phases and selection of DBC. The method is divided in three phases, that are divided in activities orienting by actions that seek to the quality of the information for a socket of decision in an automated and oriented way for defined evaluation criteria during the Requirements Engineering. This approach divide the requirements in three levels: Fundamental, Contractual and Desirable. The functional and no-functional requirements are treated in an equalitarian way. / Este trabalho apresenta diretrizes para avaliação e seleção de produtos COTS (Commercial- Off-The-Shelf). Apresenta-se uma metodologia para o Desenvolvimento Baseado em COTS (DBC) na Engenharia de Requisitos, abordando-se as fases de avaliação e seleção do DBC. O método está dividido em três fases, que por sua vez estão divididas em atividades direcionadas por ações que visam à qualidade das informações para uma tomada de decisão de forma automatizada e orientada por critérios de avaliação definidos durante a Engenharia de Requisitos. Esta abordagem divide os requisitos em três níveis, são eles: Fundamental, Contratual e Desejável. Os requisitos funcionais e não-funcionais são tratados de forma igualitária.

Formal specifications describe the behaviour of object-oriented systems precisely, with the intent to capture all properties necessary for correctness. Relationships between objects, and in a broader sense the relationship between whole components, may not be adequately captured by specifications. One critical component of specifications having a role in relationships are invariants which define a constraint between multiple objects. If an object's invariant relies on external objects for its conditions, correct operations which abide by their specifications modifying these external objects may violate the constraint. Such an invariant defines a relationship between multiple objects which is unsound since it does not adequately describe the responsibilities which the objects in the relationship have to each other. The root cause of this correctness loophole is the failure of specifications to capture such relationships adequately as well as their correctness requirements. This thesis addresses this shortcoming in a number of ways, both for individual objects in a sequential environment, and between concurrent components which are defined as specialized object types. The proposed Colleague Technique [29] defines sound invariants between two object types using classical Design-by-Contract [35] methodologies. Additional invariant conditions introduced through the technique ensure that no correct operation may produce a post-state which does not satisfy all invariants satisfied by the pre-state. Relationships between objects, as well as their correct specification and management, are the subjects of this thesis. Those relationships between objects which can be described by invariants are made sound with the Colleague Technique, or the lightweight ownership type system that accompanies it. Behavioural correctness beyond these can be addressed with specifications in a similar manner to sequential systems without concurrency, in particular with the use of runtime assertion checking [11].

Made available in DSpace on 2015-05-14T12:36:52Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 2070301 bytes, checksum: e15a4fc1a4f27fd39d2a55b1400d522b (MD5) Previous issue date: 2014-08-30 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / The great difficulty of selecting software components is still an obstacle to achieving the success of Component-Based Development (CBD). With the growing market for components, the tendency is always to increase the number of options for assembling applications in different contexts, making it impractical to manual selection. Dealing with a problem of gigantic and complex search space, it is required automation performed by optimization techniques. The proposed approach aims to automate the process of selecting components using techniques of Search-Based Software Engineering (SBSE), whose optimization technique is driven by structural metrics (i.e., connections between components of a software architecture) and information reuse (i.e., aggregated values to the component itself). The metrics used in this component selection context are intended to assess the structural perspective of an architectural instance, since they predict possible integration problems between implementations of components produced by third parties. Note that other proposals ignore this perspective and focus only on the component itself. In addition, reuse information can bring an alternative to represent the perception of the developers about the quality attributes of the software components in a reuse scenario as: the degree of consumers' satisfaction who have already purchased this component and the number of downloads of it. The proposed evaluation is carried out through experiments, which are validated by applying statistical tests. / A grande dificuldade de selecionar componentes de software ainda é um obstáculo para alcançar o sucesso do Desenvolvimento Baseado em Componentes (DBC). Com o crescimento do mercado de componentes, a tendência é sempre aumentar o número de opções para montagem de aplicações em diferentes contextos, tornando impraticável a seleção manual. Tratando de um problema com gigantesco espaço de busca e complexo, é requerida a automatização efetuada por técnicas de otimização. O trabalho proposto visa automatizar o processo de seleção de componentes utilizando técnicas da Engenharia de Software Baseada em Busca (ESBB), cuja técnica de otimização é orientada por métricas estruturais (avaliam as conexões entre componentes de uma arquitetura de software) e informações de reúso (i.e., valores correspondentes ao reúso de software agregados ao próprio componente). As métricas utilizadas neste contexto de seleção de componentes têm o propósito de avaliar a perspectiva estrutural de uma instância arquitetural, já que elas preveem possíveis problemas de integração entre implementações de componentes produzidas por terceiros, além de que muitos problemas ignoram essa perspectiva e só focam no componente em si. Já as informações de reúso trazem consigo uma alternativa para representar a percepção dos desenvolvedores sobre os atributos de qualidade dos componentes de software em cenários de reúso, tais como: o grau de satisfação dos consumidores que já adquiriram tal componente e o número de downloads do mesmo. A avaliação da proposta é conduzida através de experimentos, que são validados aplicando testes estatísticos.