The goal of this report is the development of a PSpice based modeling platform for the evaluation of power IGBT modules to be used in HVDC and FACTS applications. The use of simulation tools is of great value in the process of developing new power electronic devices and new converter topologies. By means of this proper model platform, new design ideas and better understanding of devices behavior and related physical phenomena of the modules can be easily estimated and the outcome is reducing the demand of extensive laboratory testing. Particularly important is the choice of a proper model capable of fast simulation times and adequate accuracy, while a challenging issue is to guarantee the convergence of such models given the hard nonlinearities and multiple cross-references involved. The choice of a Spice based simulation platform consisting in a circuitously based model, allows us to evaluate the characteristics of each module as a function of parameters like a dc-voltage, load current, stray inductance and gate driving.

As the demand for portable electronic devices increase, the need to replace off-chip discrete devices with on-chip devices is imperative. Inductors are one such passive device that is widely used in low noise amplifiers, oscillators, etc. Current on-chip spiral inductors suffer from large parasitics and area for a meager value of inductance and quality factor. The need to overcome these issues has led to the development inductors with new geometries housing magnetic cores that show an enhanced inductance compared to the air core coil. In this thesis, we discuss the design of a three-dimensional spiral inductor with a Co-Fe nanoparticle core that will be fabricated as per the process rules set by VT MT SPL. The changes in the value of the inductance, resistance, quality factor and parasitics are studied for varying number of turns of the coil, thickness of the coil, spacing between turns and different materials used as the coil. An optimum design incorporating the least parasitics and reasonable inductance is proposed. / Master of Science

Les travaux de thèse visent à optimiser la linéarité des HEMT GaN et intervenir dans la mise en oeuvre d’un banc load-pull multi-tons (MTLP). L’optimisation repose sur la simulation électrique d’un modèle du transistor et la quantification des effets des non-linéarités du modèle, les effets des parasites basses-fréquences soustraits au préalable. La mesure MTLP unifie potentiellement les caractérisations en linéarité traditionnelles. La réalisation de l’environnement de simulation permettant de simuler un modèle et la configuration MTLP accompagnent ces travaux. La modélisation considère un développement 8x0.25x75μm² et un point de repos (30V, 60mA). La caractéristique intrinsèque Id(Vgs, Vds) est identifiée de façon relativement rigoureuse et l’interprétation selon laquelle deux cadences d’émission (longue/rapide) et un seuil d’activation en Vds caractérisant les pièges longs est renforcée. Les modèles petit-signal et thermique sur Cgd sont directement extraits de paramètres [S] BF. L’émulation télécom est réalisé avec un signal à 8 raies pures irrégulièrement espacées satisfaisant aux conditions : PAPR=8.5 dB et loi gaussienne des composantes I,Q(t). Le choix des fréquences nous prémunit de l’interférence parmi IM3,5 (intermodulation d’ordre 3,5) et raies principales et l’acquisition (amplitude/phase) couvrent raies principales et d’IM3 de de relation fi + fj-fk et 2 fi-fj. Le critère de linéarité est celui du C/13 (taux d'intermodulation d'ordre3). Les signaux mono-/bi-porteuses sont parallèlement mis en oeuvre pour mesurer et comparer la linéarité de technologies GH25, GH50 et concurrente à 2 et 4 GHz. La nonlinéarité parasite est quantifiée sur la puissance disponible à l’entrée ( 1/2|a1|2 ) et l’analyse conjointe des caractéristiques temporelles d’enveloppe est proposée. / The PhD aims at optimizing the linearity of GaN HEMT in addition to the development and exploitation of a multi-tone load-pull bench (MTLP). The optimization is commonly based on electrical simulations implementing a model of the transistor and telecom signal and consists of identifying the influence of each non-linearity while annihilating low-frequency parasitics effects (models). The MTLP experiment has some capability to unify the classical linearity characterizations. The electrical simulation consistent with MTLP data is also suggested. The modelling focus on a 8x0.25x75μm² HEMT GaN sample and a (30V, 60mA) quiescent bias. The intrinsic Id(Vgs,Vds) characteristic is more accurately evaluated and more consistent look the interpretation that two types of emission time-scale (fast and long) plus a Vds trigger threshold (15V) characterizing the ‘long’ trap. The small-signal and the thermal model related to Cgd are straightforwardly extracted from low-frequency [S] parameters. A signal composed of unequally-spaced 8 tones has a PAPR=8.5 dB and Gaussian statistical rule of its I,Q(t) components (telecom properties). The frequency set implies no interferences among IM3,5 (3rd,5th order intermodulation ratio) and main tones. Power-wave acquisition cover the main tones and IM3 satisfying fi + fj-fk and 2 fi-fj. The C/I3 (3rd order carrier-to-intermodulation ratio) is the main linearity criterion. CW (Continuous Wave) and two-tone signals are also put into operation to survey and compare the linearity performances of GH25, GH50 and acompetitor. The parasitic non-linearity is quantified ( 1/2|a1|2 ) and the time-domain analysis give rise to interpretation about how trap effect may interact with linearity.

The non-isolated POL converters are widely used in computers, telecommunication systems, portable electronics, and many other applications. These converters are usually constructed using discrete components, and operated at a lower frequency around 200 ~ 600 kHz to achieve a decent efficiency at the middle of 80's%. The passive components, such as inductors and capacitors, are bulky, and they occupy a considerable foot-print. As the power demands increase for POL converters and the limited real estate of the mother board, the POL converters must be made significantly smaller than what they have demonstrated to date. To achieve these goals, two things have to happen simultaneously. The first is a significant increase in the switching frequency to reduce the size and weight of the inductors and capacitors. The second is to integrate passive components, especially magnetics, with active components to realize the needed power density. Today, this concept has been demonstrated at a level less than 5A and a power density around 300-700W/in3 by using silicon-based power semiconductors. This might address the need of small hand-held equipment such as PDAs and smart phones. However, it is far from meeting the needs for applications, such as netbook, notebook, desk-top and server applications where tens and hundreds of amperes are needed. After 30 years of silicon MOSFET development, the silicon has approached its theoretical limits. The recently emerged GaN transistors as a possible candidate to replace silicon devices in various power conversion applications. GaN devices are high electron mobility transistors (HEMT) and have higher band-gap, higher electron mobility, and higher electron velocity than silicon devices, and offer the potential benefits for high frequency power conversions. By implementing the GaN device, it is possible to build the POL converter that can achieve high frequency, high power density, and high efficiency at the same time. GaN technology is in its early stage; however, its significant gains are projected in the future. The first generation GaN devices can outperform the state-of-the-art silicon devices with superior FOM and packaging. The objective of this work is to explore the design of high frequency, high power density 12 V input POL modules with GaN devices and the 3D integration technique. This work discusses the fundamental differences between the enhancement mode and depletion mode GaN transistors, the effect of parasitics on the performance of the high frequency GaN POL, the 3D technique to integrate the active layer with LTCC magnetic substrate, and the thermal design of a high density module using advanced substrates with improved thermal conductivity. The hardware demonstrators are two 12 V to 1.2 V highly integrated 3D POL modules, the single phase 10 A module and two phase 20 A module, all built with depletion mode GaN transistors and low profile LTCC inductors. / Master of Science

No description available.

Exploring RF models for an integrated power electronics module (IPEM) is crucial to analyzing and predicting its EMI performance. This thesis deals with the parasitics extraction approach for an active IPEM in a frequency range of 1MHz through 30MHz. Based on the classic electromagnetic field theory, the calculating equations of DC and AC parameters for a 3D conducting structure are derived. The influence of skin effect and proximity effect on AC resistances and inductances is also investigated at high frequencies. To investigate RF models and EMI performance of the IPEM, a 1kW 1MHz series resonant DC-DC converter (SRC) is designed and fabricated in this work. For extracting the stray parameters of the built IPEM, two main software simulation tools ¡ª Maxwell Quick 3D Parameter Extractor (Maxwell Q3D) and Maxwell 3D Field Simulator (Maxwell 3D), prevailing electromagnetic simulation products from Ansoft Corporation, are introduced in this study. By trading off between the numerical accuracy and computational economy (CPU time and consumption of memory size), Maxwell Q3D is chosen in this work to extract the parameters for the full bridge IPEM structure. The step-by-step procedure of using Maxwell Q3D is presented from pre-processing the 3D IPEM structure to post-processing the solutions, and exporting equivalent circuit for PSpice simulations as well. RF modeling of power MOSFETs is briefly introduced. In order to verify extracted parameters, in-circuit impedance measurements for the IPEM using Agilent 4294A Impedance Analyzer together with Agilent 42941A probe are then followed. Measured results basically verify the extracted data, while the discrepancy between measured results and simulated results is also analyzed. / Master of Science

Avec l'arrivée des systèmes radio mobiles de troisième et de quatrième génération, les standards de communications ont tendance à occuper plus de bande pour pouvoir assurer des services de voix, de données et de multimédia. En parallèle, le terminal mobile doit être reconfigurable pour couvrir à la fois le service cellulaire et la connectivité de données. Dans ce contexte, la tendance est d'intégrer les fonctions radio et bandes de base sur le même substrat en utilisant la technologie CMOS afin de réduire la surface, le coût de fabrication et la consommation des terminaux sans fils. Récemment, de nouvelles architectures de réception radio dites " échantillonnées " sont apparues (TexasInstruments, STMicroelectronics, UCLA). Dans ce cas, l'échantillonnage est fait directement sur le signal RF et la majorité du traitement de signal se fait en temps-discret par des capacités commutées. L'évolution de la technologie CMOS et la miniaturisation des transistors rendent la conception analogique de plus en plus difficile (capacités parasites, bruit, linéarité, etc.). De nouveaux effets parasites apparaissent comme la fuite de grille qui inquiète désormais les technologues et les concepteurs de circuits. D'un autre côté, des contraintes de dynamique surgissent avec la diminution des tensions d'alimentation et le bruit des circuits numériques de plus en plus denses augmente considérablement. Le but de ce travail de thèse est de répondre à la question de la portabilité de la solution échantillonnée, en étudiant l'impact des différents effets parasites cités précédemment sur les performances radio de la solution. Ainsi, les critères de portabilité qui sont considérés sont la reconfigurabilité, l'immunité aux effets parasites, l'adaptation à la baisse des tensions d'alimentation, la surface, la consommation et la facilité de conception. Ce travail de thèse a été basé sur des études théoriques et sur des simulations d'une solution échantillonnée de réception radio. Afin d'affronter réellement les problématiques de portabilité, un portage d'une chaîne de réception échantillonnée Wi-Fi/WiMAX de CMOS 65nm à 45nm a été réalisé. Les résultats de mesures obtenus sur ce circuit donnent une grande confiance vis-à-vis des performances radio de la solution échantillonnée et constituent un premier élément de réponse concret à la question de portabilité étudiée.

No description available.

Capacitive crosstalk noise can affect the delay of a switching signal or induce a glitch on a static signal causing timing violations or chip failure. Crosstalk noise depends on coupling parasitics, driver strength, signal timing characteristics, and signal transition patterns. Layout level crosstalk analysis techniques are generally pessimistic and computationally expensive for large designs due to lack of design flexibility at lower-levels of design hierarchy. The architectural decisions such as type of interconnect architecture, number of storage and execution units, network of communicating units, data bus width, etc., have a major impact on the quality of design attributes such as area, speed, power, and noise. To address all these concerns, we propose a high-level synthesis framework to optimize for worst-case crosstalk patterns on coupled nets, a floorplan driven high-level synthesis framework to minimize coupling capacitance, and an on-chip technique to dynamically detect and eliminate worst-case crosstalk pattern on bus-based macro-cell designs. Due to Miller coupling effect, the switching activity pattern on adjacent nets may increase the effective capacitance seen by a victim net and thereby it may cause a worst-case signal delay on the victim net. However, signal activity pattern on coupled nets are dependent on data correlations which in turn depend on resource sharing. The resource sharing in turn depends on scheduling, allocation, and binding during high-level synthesis flow. Therefore, we propose a Simulated Annealing (SA) based design space exploration of HLS design subspace, bus line re-ordering, and encoding subspaces to optimize for worst-case crosstalk pattern in bus-based macro-cell designs. We demonstrate that the proposed framework will aid layout level techniques in eliminating false positive violations. We also propose an SA based algorithm to explore floorplan and HLS subspaces to optimize coupling capacitances in bus-based macro-cell designs. We have integrated an RTL floorplanner in HLS flow to estimate coupling capacitances between bus lines. Crosstalk analysis using Cadence Celtic shows that the designs generated by the proposed framework results in less number of crosstalk violations compared to designs generated through traditional ASIC design flow. We also propose an on-chip crosstalk detection and elimination technique that dynamically detects and eliminates worst-case crosstalk pattern with minimum area penalty compared to other layout level techniques reported in the literature.

No description available.