Design techniques for heterogeneous three-dimensional (3-D) integrated circuits are developed in this thesis. Heterogeneous 3-D integration is a platform for multifunctional, high performance, and low power electronics. For the advancement of heterogeneous 3-D ICs, contactless solutions are investigated to implement inter-tier communication between tiers manufactured with disparate processes and heterogeneous technologies. Two challenges for the development of contactless inter-tier communication are addressed, the design of energy efficient, heterogeneous inductive link transceivers and the impact of crosstalk noise due to the on-chip spiral inductors. Inter-tier communication between circuits fabricated with disparate technologies requires transceivers capable of operating at dissimilar voltages. A low power transceiver design methodology is proposed exploiting the difference in the core voltage between disparate manufacturing processes in a 3-D system in package. A transceiver is designed to provide inter-tier communication between a sensing layer, designed in a commercial 0.35 Âμm process and a processing layer, designed in an advanced 65 nm process. A significant gain in the power consumed by the transceiver is shown compared to equivalent state-of-the-art prototypes, profiting by the tradeoff between the core voltage and sensing ability of the transceiver circuit in each process. Due to their wireless nature, however the use of inductive links introduces crosstalk noise due to the coupling between the on-chip inductor and on-chip interconnects in the vicinity of the inductor. The noise caused by the inductor on the power distribution network of an integrated system is explored, analysed, and modelled through electromagnetic simulations. The spatial distribution of the noise is described for several power distribution topologies to determine the preferred placement solution for the power and ground network in the vicinity of the inductor, considering the impact on other sources of noise, such as the resistive drop. Depending upon the power distribution network topology, the induced noise can be reduced up to 70% when the additional noise caused by the inductive link is considered by the routing algorithm. Additionally, a methodology utilising an analytic model is proposed for the evaluation of the crosstalk noise without resorting to electromagnetic simulations. A closed-form magnetostatic model is developed to assess the mutual inductance between the on-chip inductor and the power distribution network. Utilising the mutual inductance model, the crosstalk noise is evaluated with SPICE simulations. A signifcant benefit in speedup is achieved, up to four orders of magnitude for determining the mutual inductance and up to 4.7× for the assessment of the crosstalk noise. The accuracy of the model is within 10% of the electromagnetic simulation.

A combined solution of the Feed-Forward Equalizer (FFE) and Near-End Crosstalk (NEXT) noise cancellation technique was suggested. The techniques increase data throughput and improve link quality in the 20-in FR4 legacy backplane application. Backplane channel loss and coupling noise were measured and characterized to develop the corresponding behavioral channel model. The receiver-side FFE with 4-tap Finite Impulse Response (FIR) filter structure was adopted as the optimum equalizer topology. The 4-tap FIR filter consists of tap delay line with tap-spacing 33 ps and linear tap-gain amplifiers. The tap coefficients were calculated with the Minimum-Mean-Squared-Error (MMSE) algorithm. A 0.18-um CMOS 4-tap FIR filter IC was designed and fabricated. The experiment results showed the 20-Gbit/sec 4-PAM and 10-Gbit/sec NRZ signal were successfully equalized for the 20-in FR4 legacy backplane channel. Moreover, the suggested NEXT noise cancellation technique consists of coarse- and fine-cancellation stages. The 0.18-um CMOS building block ICs such as 7-tap FIR filter, tunable active Pole-Zero (PZ) filter, and a temporal alignment delay line were fabricated. The experiment results showed that 6-dB Signal-to-Noise Ratio (SNR) improvement was achieved by the developed NEXT noise cancellation technique.

Capacitive crosstalk noise can affect the delay of a switching signal or induce a glitch on a static signal causing timing violations or chip failure. Crosstalk noise depends on coupling parasitics, driver strength, signal timing characteristics, and signal transition patterns. Layout level crosstalk analysis techniques are generally pessimistic and computationally expensive for large designs due to lack of design flexibility at lower-levels of design hierarchy. The architectural decisions such as type of interconnect architecture, number of storage and execution units, network of communicating units, data bus width, etc., have a major impact on the quality of design attributes such as area, speed, power, and noise. To address all these concerns, we propose a high-level synthesis framework to optimize for worst-case crosstalk patterns on coupled nets, a floorplan driven high-level synthesis framework to minimize coupling capacitance, and an on-chip technique to dynamically detect and eliminate worst-case crosstalk pattern on bus-based macro-cell designs. Due to Miller coupling effect, the switching activity pattern on adjacent nets may increase the effective capacitance seen by a victim net and thereby it may cause a worst-case signal delay on the victim net. However, signal activity pattern on coupled nets are dependent on data correlations which in turn depend on resource sharing. The resource sharing in turn depends on scheduling, allocation, and binding during high-level synthesis flow. Therefore, we propose a Simulated Annealing (SA) based design space exploration of HLS design subspace, bus line re-ordering, and encoding subspaces to optimize for worst-case crosstalk pattern in bus-based macro-cell designs. We demonstrate that the proposed framework will aid layout level techniques in eliminating false positive violations. We also propose an SA based algorithm to explore floorplan and HLS subspaces to optimize coupling capacitances in bus-based macro-cell designs. We have integrated an RTL floorplanner in HLS flow to estimate coupling capacitances between bus lines. Crosstalk analysis using Cadence Celtic shows that the designs generated by the proposed framework results in less number of crosstalk violations compared to designs generated through traditional ASIC design flow. We also propose an on-chip crosstalk detection and elimination technique that dynamically detects and eliminates worst-case crosstalk pattern with minimum area penalty compared to other layout level techniques reported in the literature.

The continuous scaling of interconnect wires in deep submicron (DSM)circuits result in increased interconnect delay, power and crosstalk noise. In this dissertation, we address the problem of multi-metric optimization at post layout level in the design of deep submicron designs and develop a game theoretic framework for its solution. Traditional approaches in the literature can only perform single metric optimization and cannot handle multiple metrics. However, in interconnect optimization, the simultaneous optimization of multiple parameters such as delay, crosstalk noise and power is necessary and critical. Thus, the work described in this dissertation research addressing multi-metric optimization is an important contribution.Specifically, we address the problems of simultaneous optimization of interconnect delay and crosstalk noise during (i) wire sizing (ii) gate sizing (iii) integrated gate and wire sizing, and (iv) gate sizing considering process variations. Game the ory provides a natural framework for handling conflicting situations and allows optimization of multiple parameters. This property is exploited in modeling the simultaneous optimization of various design parameters such as interconnect delay, crosstalk noise and power, which are conflicting in nature. The problem of multi-metric optimization is formulated as a normal form game model and solved using Nash equilibrium theory. In wire sizing formulations, the net segments within a channel are modeled as the players and the range of possible wire sizes forms the set of strategies. The payoff function is modeled as (i) the geometric mean of interconnect delay andcrosstalk noise and (ii) the weighted-sum of interconnect delay, power and crosstalk noise, in order to study the impact of different costfunctions with two and three metrics respectively. In gate sizing formulations, the range of possible gate sizes is modeled as the set of strategies and the payoff function is modeled as the geome tric mean of interconnect delay and crosstalk noise. The gates are modeled as the players while performing gate sizing, whereas, the interconnect delay and crosstalk noise are modeled as players for integrated wire and gate sizing framework as well as for statistical gate sizing under the impact of process variations.The various algorithms proposed in this dissertation (i) perform multi-metric optimization (ii) achieve significantly better optimization and run times than other methods such as simulated annealing, genetic search, and Lagrangian relaxation (iii) have linear time and space complexities, and hence can be applied to very large SOC designs, and (iv) do not require rerouting or incur any area overhead. Thecomputational complexity analysis of the proposed algorithms as well as their software implementations are described, and experimental results are provided that establish the efficacy of the proposed algorithms.