Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die variations have become dominant and it is imperative to model them to obtain accurate timing analysis results. In addition, intra-die process variations are spatially correlated due to pattern dependencies in the manufacturing process. Any statistical static timing analysis (SSTA) tool is incomplete without a model for signal crosstalk, as critical path delays can increase or decrease depending on the switching of capacitively coupled nets. The coupled signal timing in turn depends on the process variations. This work describes an SSTA tool that models signal crosstalk and spatial correlation in intra-die process variations, along with gradients and inter-die variations.

A test chip design is presented for the characterization of process variations and Through Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de- signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries process through CMC microsystems. The test chip takes advantage of the architecture of 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a device array density of 40.94 m2 per device. The design also has a high spatial resolution and measurement delity compared to similar 2D variation characterization test structures. Background leakage subtraction and radial ltering are two techniques that are ap- plied to the chip's measurements to reduce its error further for subthreshold device current measurements and stress-induced mobility measurements, respectively. Experimental mea- surements are be taken from the chip using a custom PCB measurement setup once the chip has returned from fabrication.

A test chip design is presented for the characterization of process variations and Through Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de- signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries process through CMC microsystems. The test chip takes advantage of the architecture of 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a device array density of 40.94 m2 per device. The design also has a high spatial resolution and measurement delity compared to similar 2D variation characterization test structures. Background leakage subtraction and radial ltering are two techniques that are ap- plied to the chip's measurements to reduce its error further for subthreshold device current measurements and stress-induced mobility measurements, respectively. Experimental mea- surements are be taken from the chip using a custom PCB measurement setup once the chip has returned from fabrication.

The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of these variations on logic cell and interconnect delays has introduced challenges to both circuit performance (timing)verification and optimization. In order for us to fully take advantage of the benefits of technology scaling, it is essential that ``variation-aware''techniques for performance verification and optimization be developed and used in modern design flows. In this thesis such techniques for both performance verification and optimization are presented. First, we present a fast method for finding the worst-case slacks over all process and environmental corners. This method uses the standard set of PVT corners available in industry, and provides large runtime gains while maintaining a high degree of accuracy. After that, we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delays at every point in the parameter space, by reporting all paths that can become critical. This method employs parameterized static timing analysis (PSTA) variability models, and allows one to easily examine local robustness to parameters in different regions of the parameter space. Next, we introduce an optimization method that alters clock network lines so that a circuit meets its timing constraints at all PVT settings under PSTA variability models. This is formulated as a Linear Program (LP), which is based on a clock skew optimization formulation, and as a result it can be solved efficiently. Finally, we present a method that uses characterized, pre-silicon, PSTA variational timing models to identify speedpaths that can best explain the observed delay measurements during silicon debug. This is a crucial step, required for both ``fixing'' failing paths and for accurate learning from silicon data.

The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of these variations on logic cell and interconnect delays has introduced challenges to both circuit performance (timing)verification and optimization. In order for us to fully take advantage of the benefits of technology scaling, it is essential that ``variation-aware''techniques for performance verification and optimization be developed and used in modern design flows. In this thesis such techniques for both performance verification and optimization are presented. First, we present a fast method for finding the worst-case slacks over all process and environmental corners. This method uses the standard set of PVT corners available in industry, and provides large runtime gains while maintaining a high degree of accuracy. After that, we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delays at every point in the parameter space, by reporting all paths that can become critical. This method employs parameterized static timing analysis (PSTA) variability models, and allows one to easily examine local robustness to parameters in different regions of the parameter space. Next, we introduce an optimization method that alters clock network lines so that a circuit meets its timing constraints at all PVT settings under PSTA variability models. This is formulated as a Linear Program (LP), which is based on a clock skew optimization formulation, and as a result it can be solved efficiently. Finally, we present a method that uses characterized, pre-silicon, PSTA variational timing models to identify speedpaths that can best explain the observed delay measurements during silicon debug. This is a crucial step, required for both ``fixing'' failing paths and for accurate learning from silicon data.

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic systems for long-haul applications, however, in the past decade there has been a trend towards multi-Gb/s backplane interconnects. The integration of clock and data recovery (CDR) circuits into monolithic integrated circuits (ICs) is attractive as it improves performance and reduces the system cost, however it also introduces new challenges, one of which is robustness. In serial data communication systems the CDR circuit is responsible for recovering the data from an incoming data stream. In recent years there has been a great deal of research into integrating CDR circuits into monolithic ICs. Most research has focused on increasing the bandwidth of the circuits, however in order to integrate multi-Gb/s CDR circuits robustness, as well as performance, must be considered. In this thesis CDR circuits are analyzed with respect to their robustness. The phase detector is a critical block in a CDR circuit and its robustness will play a significant role in determining the overall performance in the presence of process non-idealities. Several phase detector architectures are analyzed to determine the effects of process non-idealities. Static phase offsets are introduced as a figure of merit for phase detectors and a mathematical framework is described to characterize the negative effects of static phase offsets on CDR circuits. Two approaches are taken to improve the robustness of CDR circuits. First, calibration circuits are introduced which correct for static phase offsets in CDR circuits. Secondly, phase detector circuits are introduced which have been designed to optimize both performance and robustness. Several prototype chips which implement these schemes will be described and measured results will be presented. These results show that while CDR circuits are vulnerable to the effects of process non-idealities, there are circuit techniques which can mitigate many of these concerns.

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic systems for long-haul applications, however, in the past decade there has been a trend towards multi-Gb/s backplane interconnects. The integration of clock and data recovery (CDR) circuits into monolithic integrated circuits (ICs) is attractive as it improves performance and reduces the system cost, however it also introduces new challenges, one of which is robustness. In serial data communication systems the CDR circuit is responsible for recovering the data from an incoming data stream. In recent years there has been a great deal of research into integrating CDR circuits into monolithic ICs. Most research has focused on increasing the bandwidth of the circuits, however in order to integrate multi-Gb/s CDR circuits robustness, as well as performance, must be considered. In this thesis CDR circuits are analyzed with respect to their robustness. The phase detector is a critical block in a CDR circuit and its robustness will play a significant role in determining the overall performance in the presence of process non-idealities. Several phase detector architectures are analyzed to determine the effects of process non-idealities. Static phase offsets are introduced as a figure of merit for phase detectors and a mathematical framework is described to characterize the negative effects of static phase offsets on CDR circuits. Two approaches are taken to improve the robustness of CDR circuits. First, calibration circuits are introduced which correct for static phase offsets in CDR circuits. Secondly, phase detector circuits are introduced which have been designed to optimize both performance and robustness. Several prototype chips which implement these schemes will be described and measured results will be presented. These results show that while CDR circuits are vulnerable to the effects of process non-idealities, there are circuit techniques which can mitigate many of these concerns.

As we move under the aegis of the Moore's law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node.

Driven by the need for faster devices and higher transistor densities, technology trends have pushed transistor dimensions into the deep sub-micron regime. This continued scaling, however, has led to many challenges facing digital integrated circuits today. One important challenge is the increased variations in the underlying process and environmental parameters, and the significant impact of this variability on circuit timing and leakage power, making it increasingly difficult to design circuits that achieve a required specification. Given these challenges, there is a need for computer-aided design (CAD) techniques that can predict and analyze circuit performance (timing and leakage) accurately and efficiently in the presence of variability. This thesis presents new techniques for variation-aware timing and leakage analysis that address different aspects of the problem. First, on the timing front, a pre-placement statistical static timing analysis technique is presented. This technique can be applied at an early stage of design, when within-die correlations are still unknown. Next, a general parameterized static timing analysis framework is proposed, which supports a general class of nonlinear delay models and handles both random (process) parameters with arbitrary distributions and non-random (environmental) parameters. Following this, a parameterized static timing analysis technique is presented, which can capture circuit delay exactly at any point in the parameter space. This is enabled by identifying all potentially critical paths in the circuit through novel and efficient pruning algorithms that improve on the state of art both in theoretical complexity and runtime. Also on the timing front, a novel distance-based metric for robustness is proposed. This metric can be used to quantify the susceptibility of parameterized timing quantities to failure, thus enabling designers to fix the nodes with smallest robustness values in order to improve the overall design robustness. Finally, on the leakage front, a statistical technique for early-mode and late-mode leakage estimation is presented. The novelty lies in the random gate concept, which allows for efficient and accurate full-chip leakage estimation. In its simplest form, the leakage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time.

Driven by the need for faster devices and higher transistor densities, technology trends have pushed transistor dimensions into the deep sub-micron regime. This continued scaling, however, has led to many challenges facing digital integrated circuits today. One important challenge is the increased variations in the underlying process and environmental parameters, and the significant impact of this variability on circuit timing and leakage power, making it increasingly difficult to design circuits that achieve a required specification. Given these challenges, there is a need for computer-aided design (CAD) techniques that can predict and analyze circuit performance (timing and leakage) accurately and efficiently in the presence of variability. This thesis presents new techniques for variation-aware timing and leakage analysis that address different aspects of the problem. First, on the timing front, a pre-placement statistical static timing analysis technique is presented. This technique can be applied at an early stage of design, when within-die correlations are still unknown. Next, a general parameterized static timing analysis framework is proposed, which supports a general class of nonlinear delay models and handles both random (process) parameters with arbitrary distributions and non-random (environmental) parameters. Following this, a parameterized static timing analysis technique is presented, which can capture circuit delay exactly at any point in the parameter space. This is enabled by identifying all potentially critical paths in the circuit through novel and efficient pruning algorithms that improve on the state of art both in theoretical complexity and runtime. Also on the timing front, a novel distance-based metric for robustness is proposed. This metric can be used to quantify the susceptibility of parameterized timing quantities to failure, thus enabling designers to fix the nodes with smallest robustness values in order to improve the overall design robustness. Finally, on the leakage front, a statistical technique for early-mode and late-mode leakage estimation is presented. The novelty lies in the random gate concept, which allows for efficient and accurate full-chip leakage estimation. In its simplest form, the leakage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time.