This research developed a double-side power electronics packaging scheme for high temperature applications exemplified by 1200 V, 150 A silicon devices. The power modules, based on both quarter and half-bridge topologies, were assembled using sintered silver device attachment rather than conventional solder alloys. Thermomechanical stresses in the double-side architecture were mitigated with a compliant layer fabricated from elliptical silver tubes. This research presents an introduction to conventional packaging techniques and their weaknesses. These shortcomings provide the basis for a module design which improves upon module thermal management while also addressing electrical and reliability requirements. The optimum package design enhances heat dissipation with the addition of a substrate bonded to the top electrical pads of the semiconductor devices. The use of sintered silver also increases the useful application temperature by avoiding the creep failure mechanisms of solder alloys. The modules were characterized extensively to quantify thermal and electrical performance. In the case of thermal characterization, the double-side architecture required multiple testing configurations to fully understand the parallel heat flow paths. These results were compared to models constructed using finite element analysis (FEA). The FEA models were also utilized for measurement of strains in multiple package designs to better determine the effects of increased compliance on the relative package cycling lifetime. These lifetimes were then assessed, in part, using experimental passive and cycling tests on functional double-side packages. The resulting power modules exhibited significant decreases in thermal resistance when they are cooled, as designed, from both sides of the module. Even single sided cooling options reveal significant advantages and transient thermal impedance was found to be significantly lower. Power module models revealed the compliant layer was successful in reducing the device shear stresses which was experimentally validated through the use of DC power stage testing. It was found, through double pulse testing and electrical modeling, that parasitic inductances were reduced by utilizing planar bonding and planar symmetrical traces. Finally, modeling of the double-side package with added tube compliance revealed a decrease in plastic and shear strains when compared to other single and double-side package designs. This reduction directly translates to increased cycling lifetime using well known strain based fatigue models. / Ph. D.

With the potential to improve upon silicon (Si ) based power electronics exhausted, the push for improvement now lies with wide bandgap (WBG) materials like gallium nitride (GaN). With a larger bandgap, higher electron mobility, and higher electrical field strength than Si, GaN high electron mobility transistors (HEMTs) can have lower on-state losses and higher switching frequencies in a smaller package. This makes GaN HEMTs an attractive choice for compact, high efficiency power devices. However, the package designs used for Si cannot be used for GaN HEMTs, requiring novel, chip-scale designs that are optimized for low electrical parasitics and low thermal resistance. Recent Center for Power Electronics (CPES) research culminated in a printed circuit board-direct bonded copper (PCB-DBC) hybrid package to house a 650 V, 150 A GaN HEMT. Called the PCB-Interposer-on-DBC package, it utilizes a DBC for heat extraction while using vertical pin interconnects to minimize electrical parasitics. Previous work did not investigate the design's locations of expected failure or reliability. With thermally generated mechanical fatigue a consistent cause of electronics failure, it must be investigated for the design to move beyond the prototyping phase. Thermo-mechanical fatigue failure is the brittle fracture of bonds caused by thermally induced warpage. The thermal warpage is the consequence of the bonded package components having a coefficient of expansion (CTE) mismatch while being subjected to temperature changes during operation. Multiphysics simulation software have previously quantified the fatigue placed on bonds exposed to these cyclic conditions, with a common metric being the volume-averaged inelastic strain energy density gained per cycle (ΔWavg). ΔWavg can identify which bonds are subjected to the greatest amount of fatigue and will thus fail first, and then quantify the effect of design alterations on those vulnerable bonds. A common design alteration seen in solder ball packaging is adding a polymeric material that encapsulates the bonds. If the polymer has a CTE like that of the package substrates and an elastic modulus (E) exceeding 1 GPa, it constrains the thermal warpage and lowers bond fatigue. This thesis uses thermo-mechanical simulations to provide evidence on which bonds fail first in the package, and that material-based methods of fatigue reduction used in solder ball packing apply to this novel package. Chapter 1 explains how a desire to reduce the cost and increase the performance of electric vehicles led to the development of the PCB-Interposer-on-DBC design, and that the package's response to thermo-mechanical fatigue is unknown. The concepts of thermo-mechanical fatigue and using encapsulants to reduce it are established, along with how simulations are used to study said fatigue. Chapter 2 serves two purposes, the first being an explanation of the simulation settings and metrics used to establish the quality and assumptions used, and the second being a beginners guide on how to create these simulations. Chapter 3 identifies the most probable locations of initial package failure and identifies what encapsulants minimize ΔWavg on those locations. The sintered silver bond expected to fail first is the Internal Gate bond, and an encapsulant with the maximum possible E and 8 ppm/°C minimizes ΔWavg. The Sn60Pb40 bond expected to fail first is the External Source 4 bond and using an encapsulant with the maximum possible E and a CTE of 24 ppm/°C minimizes ΔWavg. While ΔWavg cannot determine which of the two bonds fails first as they are made of different materials, the Internal Gate is prioritized as it has a higher per-cycle fatigue and to prevent loss of the gate signal. Chapter 4 demonstrates how to perform a brief encapsulant study while ranking the expected cycles to failure when using four different encapsulant options. The first two options are to use no encapsulant or silicone gel. As the elastic modulus of silicone gels are too low to restrict or couple the thermally generated warpage, using silicone gel results in a ΔWavg comparable to using no encapsulant. The rigid encapsulant with the properties most like the optimal encapsulant identified for Internal Gate has the lowest ΔWavg¬ of the encapsulants tested. Guidelines are established for what properties an encapsulant must have to outperform said rigid encapsulant. This work uses simulations to provide evidence that encapsulant methods used in ball grid array (BGA) packaging to reduce fatigue apply to a novel GaN HEMT package. By identifying the first-failure locations of the package, establishing what existing encapsulant should be used, and what encapsulation it should eventually be replaced with, these results provide the groundwork for both experimental temperatures cycling and more complex simulations. Such work fills the gap in understanding the reliable lifetime and common failure mechanisms of the PCB-Interposer-on-DBC package. / Master of Science / In modern engineering, the cause of failure in a well-designed electronic device is typically not a single event. Rather, it is the culmination of many smaller events that each cause a minor amount of damage. This cycle of repeated, minor damage is called fatigue. When working with power or IC electronics, the most common type of fatigue occurs due to the device's changing temperature. Electronics undergo continuously changing temperatures due to the environment and their own energy losses, causing repeated cycles of heating and cooling. All materials expand upon heating and contract upon cooling , and the magnitude of this change is the coefficient of thermal expansion (CTE). Electronic devices are comprised of dissimilar materials, so disparate components will expand and contract at different rates. Holding these disparate materials together are bonds, which in the process of holding this warped structure together, also deform. This deformation causes permanent damage, which accumulates in the bonds until they break. As these bonds often serve as pathways for the electrical signal or heat extraction, their failure either degrades or breaks the electrical devices. While preventing bond fatigue is impractical, there are strategies to extend the operating lifetime. A common option used elsewhere is to encase the bonds with a polymer. If the polymer's properties are carefully selected, they can reduce the structural warpage, thereby reducing the fatigue on the bonds. Previous Center for Power Electronics (CPES) research has culminated in a new electronics device called the Printed Circuit Board-Interposer-on-Direct Bonded Copper package (PCB-Interposer-on-DBC package). While general trends suggest which bonds will fail first and what kind of polymers reduce fatigue, this information has not yet been confirmed. This thesis uses computer simulations to identify which bonds will likely fail first, and to provide evidence that existing methods for reducing fatigue are viable for this unique package. The simulations work by subjecting a 3D model to a cycle of heating and cooling, called a temperature cycle, and quantifying the damage sustained by the bonds for every cycle. Chapter 1 describes the relevant details leading to this package design, the importance of thermo-mechanical reliability in the design of electronics, and how to use simulation software to quantify reductions in bond fatigue. Chapter 2 explains how to set up these simulations and evaluate their quality. Chapter 3 identifies the initial locations of package failure and identifies what are the most optimal encapsulants to use. Chapter 4 identifies what existing encapsulant will maximize the package lifetime in experimental temperature cycling.

Interconnects in power module result in thermal interfaces. The thermal interfaces degrade under thermal cycling, or chemical loading. Moreover, the reliability of thermal interfaces can be especially problematic when the interconnecting area is large, which increases its predisposition to generate defects (voids, delamination, or nonuniform quality) during processing. In order to improve the quality of the bonding process, as well as to be able to accurately assess interface reliability, it would be desirable to have a simple, reliable, and nondestructive measurement technique that would produce a 2-d map of the interface thermal resistance across a large bonded area. Based on the transient thermal method of JEDEC standard 51-14, we developed a measurement technique that involves moving a thermal sensor discretely across a large-area bonded substrate and acquiring the interface thermal resistance at each location. As detailed herein, the sensor was fabricated by packaging an IGBT bare die. An analytical thermal model was built to investigate the effects of thermal sensor packaging materials and structural parameters on the sensitivity of the measurement technique. Based on this model, we increased the detection sensitivity of the sensor by modifying the size of the sensor substrate, the material of the sensor substrate, the size of the IGBT bare die, the size of the heat sink, and the thermal resistance between sample and the heat sink. The prototype of the thermal sensor was fabricated by mounting Si IGBT on copper substrate, after which the Al wires were ultrasonic bonded to connect the terminals to the electrodes. The sensor was also well protected with a 3-d printed fixture. Then the edge effect was investigated, indicating the application of the thermal sensor is suitable for samples thinner than the value in TABLE 2 3. The working principle of the movable thermal sensor – Zth measurement and its structure function analysis – was then evaluated by sequence. The Zth measurement was evaluated by measuring the Zth change of devices induced by degradation in sintered silver die-attach layer during temperature cycling. At the end of the temperature cycling, failure modes of the sintered silver layer were investigated by scanning electron microscope (SEM) and X-ray scanning, to construct a thermal model for FEA simulation. The simulation results showed good agreement with the measured Zth result, which verified the accuracy of the test setup. The sensitivity of structure function analysis was then evaluated by measuring thermal resistance (Rth) of interface layers with different thermal properties. The structure function analysis approach successfully detected the Rth change in the thermal interface layer. The movable thermal sensor was then applied for 2d-mapping of the interface Rth of a large-area bonded substrate. Examining the test coupons bonded by sintered silver showed good and uniform bonding quality. The standard deviation of Rth is about 0.005 K/W, indicating the 95% confidence interval is about 0.01 K/W, which is commonly chosen as the error of measurement. The sensitivity of the movable thermal sensor was evaluated by detecting defects/heat channels of differing sizes. The 2-d mapping confirmed that the thermal sensor was able to detect defect/heat channel sizes larger than 1x1 mm2. The accuracy of the sensitivity was verified by FEA simulation. Moreover, the simulated results were consistent with the measured results, which indicates that the movable sensor is accurate for assessing interface thermal resistance. In summary, based on structure function analysis of the transient thermal impedance, the concept of a movable thermal sensor was proposed for two-dimensional mapping of interface thermal resistance. (1) Preliminary evaluation of this method indicated both transient thermal impedance and structure function analysis were sensitive enough to detect the thermal resistance change of thermal interface layers. With the help of transient thermal impedance measurement, we non-destructively tested the reliability of sintered silver die-attach layer bonded on either Si3N4 AMB or AlN DBA substrates. (2) An analytical thermal model was constructed to evaluate the design parameters on the sensitivity and resolution of the movable thermal sensor. A detailed design flow chart was provided in this thesis. To avoid edge effect, requirements on thickness and materials of test coupon also existed. Test coupon with smaller thermal conductivity and larger thickness had a more severe edge effect. (3) The application of the movable sensor was demonstrated by measuring the 2-d thermal resistance map of interface layers. The results indicated for bonded copper plates (k = 400 W/mK) with thickness of 2 mm, the sensor was able to detect defect/heat channel with size larger than 1x1 mm2. / Doctor of Philosophy / Interconnects in power module result in thermal interfaces. The thermal interfaces degrade during operation and their reliability can be especially problematic when the interconnecting area is large. In order to improve the quality of the bonding process, as well as to be able to accurately assess interface reliability, it would be desirable to have a simple, reliable, and nondestructive measurement technique that would produce a 2-d map of the interface thermal resistance across a large bonded area. Based on the transient thermal method of JEDEC standard 51-14, we developed a measurement technique that involves moving a thermal sensor discretely across a large-area bonded substrate and acquiring the interface thermal resistance at each location. As detailed herein, the sensor was fabricated by packaging an IGBT bare die, which allowed us to get a 2-d map of the interface thermal resistance. A thermal model was also constructed to guide the design of the sensor, to increase its performance. Moreover, the preliminary test of the test setup was conducted to prove its feasibility for the sensor. Eventually, the sensor’s performance and application was demonstrated by measuring the 2-d thermal resistance map of the bonded interfaces.

Gesintertes Silber (SAG) stellt eines der vielversprechendsten Materialien für Hochtemperaturanwendungen in der Leistungselektronik dar. Im Vergleich zu konventionellen Loten sind die mechanischen und thermischen Vorteile enorm, allerdings hochgradig prozessabhängig. Zusammen mit den relativ zeitintensiven Ermüdungstestmethoden ist das die Ursache, dass es aktuell nur wenige Lebensdauermodelle dazu gibt. In dieser Arbeit wird am Beispiel solcher SAG-Proben ein mechanisch beschleunigter, isothermer Biegeversuch vorgestellt, welcher das Potenzial hat, die zeitkritischen Temperatur- oder Lastwechselversuche zu ersetzen. Zum Vergleich wurde ein Temperaturwechseltest als Referenzversuch durchgeführt. Hierzu wird zunächst der Stand der Technik des Silber-Sinterns aufgezeigt, wobei der Schwerpunkt auf der mechanischen Materialcharakterisierung liegt.Wo das elastische Verhalten als näherungsweise allein porositätsabhängig gelten kann, ist die inelastische Dehnung noch unzureichend untersucht. Besonders die zeitabhängige inelastische Dehnung (Kriechen) zeigt noch kein vollständig konsistentes Bild, wodurch auch die Fehlermechanismen und deren Gewichtung noch nicht grundsätzlich als geklärt gelten können. Die gängigsten Belastungstests, welche in der Literatur zu finden sind, haben schwerwiegende Nachteile. Der hohe Zeitbedarf, die teils schwer quantifizierbaren Fehlerparameter und die fehlende Einstellmöglichkeit des Verhältnisses Kriechdehnung zu plastischer Dehnung sind hier im Besonderen zu nennen. Der rein dehnungsgesteuerte Biegeversuch hat diese Nachteile nicht. Über die Biegegeschwindigkeit ließe sich der Kriechanteil nahezu beliebig erhöhen (ggf. unter Nutzung von Haltezeiten). Die Biegeversuche wurden isotherm bei fünf Temperaturen von 22◦C bis 125◦C mit je drei Amplituden und drei Biegegeschwindigkeiten durchgeführt. Schlecht gesinterte Proben machten sich reproduzierbar als Frühausfall bemerkbar, so dass sich die Methode bereits gleich zu Beginn als hervorragender Qualitätstest bewährte. In puncto Ermüdung konnte ein stabiles und reproduzierbares Ausfallverhalten in Form von vergleichbaren Weibull-Formfaktoren und Ausfallbildern in den metallografischen Schliffen gefunden werden. Mit den Daten der Biegeversuche wurde ein fehlerphysikalisches Lebensdauermodell (Coffin-Manson) aufgestellt, welches erfolgreich den Ausfall des Temperaturwechseltests als Referenzversuch vorhersagen konnte. / Sintered silver (SAG) as die attach material is one of the promising solutions to exploit the advantages of high-gap semiconductors in power electronics. The mechanical and thermal properties are far superior to solders, but severely process-dependent. Combined with the time requirements of the state of the art (SoA) fatigue test methods this is most likely the reason for the lack of profound reliability studies yet. This thesis presents an isothermal bending test, which has the ability to replace the time-consuming thermal shock test as primary fatigue experiment for physics of failure based (PoF) lifetime models. A benchmark against a conventional thermal cycling test was done. The state of the art of the silver-sintering technique will be given with focus on the mechanical material characterization. While the elastic properties are mostly porosity-dependent, the inelastic properties are insufficiently examined yet. Especially the creep does not show a consistent image, what leads to many questions regarding the failure mechanism. The most common fatigue tests in the literature do have serious disadvantages. The time-consumption is high, the failure parameter can hardly be quantified and the ratio of plasticity to creep cannot be adjusted easily. The pure mechanical bending test does not have those disadvantages. By changing the bending-speed and the addition of holding times, the creep can be adjusted almost at will. The bending-experiments were conducted at five different temperatures between 22°C and 125°C and with three bending amplitudes as well as three speeds. Insufficiently sintered samples could be identified very early. This already proofed the value of the test as a quality test. Furthermore, a stable and repeatable fatigue behaviour could be observed, what was given by stable Weibull-exponents and repeatable cross sections. A lifetime-model was established by usage of the bending-test-data, what eventually predicted successfully the lifetime of a thermal cycling reference test.

Die fortschreitende Miniaturisierung von elektronischen Systemen begleitet von steigender Leistung und Funktionalität führt zur Erhöhung der Leistungsdichte. Um diesem Trend zu entsprechen, werden neue Entwärmungskonzepte benötigt, die wiederum neuartige Materialien und Materialverbünde fordern. Ein wichtiger Aspekt dieser Arbeit ist deshalb die Konzentration auf die für den Wärmetransport entscheidenden Materialien. Diese Arbeit befasst sich mit der Entwicklung von Methoden für die umfassende thermische Charakterisierung von den verschiedenen Materialien und Materialklassen, die in der Elektronikindustrie verwendet werden. Die Messsysteme wurden so entworfen und entwickelt, dass spezifische Anwendungsbedingungen berücksichtigt werden können, keine aufwändige Probenherstellung notwendig ist und gleichzeitig eine hohe Messgenauigkeit gewährleistet ist. Es wurden vier verschiedene Messsysteme innerhalb dieser Arbeit entwickelt und realisiert, die in ihrer Gesamtheit die Charakterisierung von fast allen Package-Materialien unter gewünschten Randbedingungen ermöglichen. Zahlreiche Materialien und Effekte wurden daraufhin im Rahmen dieser Arbeit mit den entwickelten Messsystemen untersucht und diskutiert. / The continuous miniaturization of electronic systems accompanied by increasing performance and functionality leads to an increase in power density. In order to comply this trend, new heat dissipation concepts are needed which demand new materials and material composites. An important aspect of this work is therefore the concentration on the materials that are decisive for the heat flow. This thesis deals with the development of Methods for comprehensive thermal characterization of the different materials and material classes used in the electronics industry. The measuring systems have been designed and developed in such a way that they enable to take into account specific application conditions, no costly sample preparation is necessary and at the same time high measuring accuracy is ensured. Four different measuring systems were developed and realized within this work, which, in their entirety, enable the characterization of almost all package materials under desired boundary conditions. Based on this, numerous materials and effects were investigated and discussed in the context of this work with the developed measurement systems.