This dissertation presents a study of signal deskewing systems in standard CMOS technologies. The objective of this work is to understand the limitations of deskewing systems as they are applied to modern systems and present new architectures to overcome past limitations. Traditional methods for signal deskewing are
explored and the general limitations of these methods are identified. Several new architectures are proposed to address the limitations of previous techniques. The
systems will be investigated with regard to minimum resolution, programming time,
delay, maximum data rate, full scale range, and duty cycle distortion. Several other
effects that are critical to the operation of deskewing systems will also be investigated.
These effects include overshoot caused by parasitic package inductance, the impact
of capacitive terminations, and the effect of mutual inductance between traces.
To fulfill the requirements of this study, two deskewing systems are implemented
in a 0.25um process. An open-loop system for deskewing wide data busses and a
closed-loop system for deskewing a differential pair of lines are both fabricated. Both
systems are found to meet the expected performance metrics, providing validation of
the proposed techniques. Use of the proposed architectures allows the limitations of
previous methods to be overcome. The remaining work is validated through either analytical techniques, simulations, or both where appropriate.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/4969 |
| Date | 13 May 2004 |
| Creators | Atrash, Amer Hani |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
| Format | 1268142 bytes, application/pdf |
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