This thesis presents a high efficiency RF to DC converter for RFID applications. The proposed circuit has been designed in 90 nm CMOS technology using a single RF source. It exploits an internal Vth cancellation technique along with a leakage current reducer. The circuit operates in two phases: Phase 1, applies a DC voltage between gate and drain to reduce the VDS of the PMOS transistor; and Phase 2 removes this DC voltage meanwhile by pulling the drain and source terminals of the same transistor to the same potential, reducing the sub-threshold leakage current and enhancing the power conversion efficiency.
The simulation results show that high DC power up to 8.1µA can be delivered to the load. The PCE has been measured 36.3% at -14.3dBm and can be improved to 54.5% providing an impedance matching network between the source and rectifier input.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:NSHD.ca#10222/21831 |
| Date | 25 April 2013 |
| Creators | Rastmanesh, Maziar |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_US |
| Detected Language | English |
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