In this thesis, novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) TFT is developed . In the bottom gate light-shied a-Si:H TFT structure, the side edge of a-Si:H island is capped with extra deposition of heavily phosphorous-doped a-Si layer. The new structure a-Si:H TFT process steps is almost unchanged. The masksteops of fabrication new structure TFT are the same as the inverter-staggered TFT. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts between source/drain metal and a-Si:H at the edge of a-Si:H island. a-Si:H is a well-known photosensitivity material. For driving LCD the TFT must be operated with illuminated environment. It will cause the leakage current. The new TFT structure is similar to the light-shield TFT proposed by Akiyama in 1989. So the new structure TFT can not only reduce the schoktty emission leakage current but also the photo-leakage current. In addition, electrical performance of the novel a-Si:H TFT device exhibits superior effective carrier mobility, as high as 1.05 cm2/Vsec due to the enormous improvement in parasitic resistance. The impressively high performance provides the potential of our proposed a-Si:H TFT to apply for AMLCD and AMOLED technology.

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La evolución de los dispositivos MOS ha conllevado una reducción de tamaño de los mismos con el fin de mejorar sus prestaciones. Sin embargo, este continuo escalado se ha topado con un límite físico: la delgada capa aislante de SiO2 (entre otros), que fuerza la búsqueda de nuevas alternativas que permitan abastecer al exigente mercado tecnológico. En las dimensiones en las que actualmente se trabaja, del orden de nanómetros, los fenómenos cuánticos adquieren gran importancia siendo, entre otros, las corrientes de fuga uno de los principales escollos con los que se ha de lidiar. Estas corrientes provocan un aumento del consumo de potencia y disminución de la fiabilidad del dispositivo. Entre las alternativas que se perfilan como posibles opciones para reducir estas corrientes de fuga, la sustitución del hasta ahora principal aislante de la electrónica, el SiO2, por un material con una mayor constante dieléctrica, high-k (HK), ocupa una posición aventajada. Estos nuevos materiales HK permitirían mantener la misma capacidad del óxido que se obtendría usando un determinado grosor de SiO2 pero, utilizando un grosor físico mayor, reduciendo de esta manera las corrientes de fuga a través de la puerta del MOSFET. Aunque es una idea ampliamente aceptada no por ello es una tarea sencilla, ya que la introducción de estos nuevos materiales no está exenta de problemas que puedan influir en la fiabilidad del dispositivo. Por ejemplo, la morfología de los high-k y su impacto en las propiedades eléctricas del stack son factores importantes que deben ser considerados ya que pueden influir en el correcto funcionamiento del dispositivo. Los materiales bajo estudio son varios y diversos, pero gran parte de la comunidad científica apunta hacia el HfO2, o aleaciones relacionadas, y el Al2O3, como sustitutos del SiO2. Esta tesis, enmarcada en el campo de la microelectrónica, y concretamente en el estudio de la fiabilidad y caracterización eléctrica de los dispositivos MOS (Metal Óxido Semiconductor) de última generación, basados en HfO2, se centra principalmente en la evaluación, a escala nanométrica, de las propiedades morfológicas y eléctricas de dispositivos MOS fabricados con dieléctricos high-k (en concreto el HfO2). Particularmente, se analiza la influencia de la cristalización de la capa de HfO2, característica que adquiere tras haber sido sometida a un proceso de annealing durante el proceso de fabricación, en las propiedades eléctricas de la misma. Dicha cristalización puede alterar las propiedades morfológicas del material, lo que a su vez, puede repercutir en su homogeneidad eléctrica y su fiabilidad. También se ha llevado a cabo el estudio a escala nanométrica del fenómeno Resistive Switching, principal principio de operación de las memorias resistivas de acceso aleatorio (ReRAM). La evaluación del impacto de la cristalización, a escala nanométrica, se ha llevado a cabo mediante el uso de técnicas y herramientas de caracterización con resoluciones nanométricas como el AFM (Atomic Force Microscope) y técnicas relacionadas como el C-AFM (Conductive Atomic Force Microscope) o el Kelvin Probe Force Microscope (KPFM). / The evolution of MOS devices has involved an important shrinking in the transistor size with the aim of improve their benefits. However, this continuous miniaturization has found its physical limits in the thin SiO2 dielectric layer with current sizes at nanometric scale. Due to the continuous SiO2 layer thickness shrinking in a MOS transistor, tunnelling current increased more and more becoming the dominant source of device leakage. The main consequences of this leakage current enlargement are, on one hand, the consumption increase and, on the other hand, the impoverishment of the reliability of the device, which can be understood as an increment of the probability that the device failure happens for shorter times than usually. As a possible alternative to reduce the tunnelling current and also to avoid reliability issues, materials with higher dielectric constant were proposed to replace the SiO2 layer. These materials, known as high-k dielectrics, allow to obtain the equivalent performance for the capacitance with a larger physical thickness reducing, therefore, the leakage current. However, this substitution, although it sounds simple it is really a complicate issue since the introduction of new materials has associated new challenges and difficulties that must be solved. For example, the morphology of the high-k material and its impact on the electrical properties of the stack are important factors to be considered. Different materials are under study but HfO2, and related alloys, and Al2O3 are highlighted materials. This thesis, enshrined in the field of microelectronics and, specifically, in the reliability and electrical characterization of MOS devices based on high-k dielectrics, has been devoted to the analysis of nanoscale morphological and electrical properties of thin HfO2 layers with the aim to gain more insight in these new materials and related problems. Concretly, the influence of their polycrystallization on the electrical properties and breakdown (BD) of a HfO2 based gate stack has been evaluated. The study of the Resistive Random Access Memory (ReRAM) operating principle, Resistive Switching (RS), has been also investigated on MIM structures with HfO2 as dielectric. Since many of the problems associated to these materials (like, for example, their polycrystallization) and the failure mechanisms that affect the gate oxide are phenomena that have been found to have a nanometric origin, these analyses have been performed with AFM and related techniques as CAFM (Conductive Atomic Force Microscopy) or KPFM (Kelvin Probe Force Microscopy).

In recently yesrs,Thin-film transistors (TFTs) including an active layer of amorphous silicon or polycrystalline silicon have been widely employed as the pixel-driving elements of a liquid crystal display (LCD). Particularly, a-Si:H TFT is advantageous to the production of large screen displays and facilitates mass-production. a-Si:H has high photoconductivity which results in high off-state leakage currents of a-Si:H TFT under light illumination . Particularly, the off-state leakage current under light illumination is a serious problem in the projection and/or video displays which require high intensity backlight illumination.As the resolutions is higher , the TFT¡¦s performance must be higher to achieve the short charge time each line can charge. The performance includes mobility ,on current, off current, photo leakage current, threshold voltage ,and subthrehold swing. Furthermore, the to improve the mobility of thin-film transistors (TFT) to enable total integration of peripheral electronics in flat panel displays and imagers has led to recrystallized polycrystalline silicon (poly-Si) as the material of choice. However, laser recrystallized polycrystalline silicon suffers from high cost , complex processing, and significant nonuniformity over a large area. Indeed, the direct deposition of good-quality low-temperature poly films is highly desirable and constitutes a promising alternative. In this thesis, we use HDPCVD to fabricate direct deposition poly-TFT successfully.Through plasma passivation, we improve the characteristic of device. The photo-Leakage current have been reduced obviously to our device under light illumination, and is benefit to higher intensity light of large screen display. And our TFT device exhibits stable characteristics with voltage and current stress , and it¡¦s also confirmed that the device is reliable. On the characteristic of device, the direct-deposited poly TFT device exhibits higher effective carrier mobility than that of conventional one. For that reason, the high performance provides the potential of the direct-deposited poly TFT to apply for AMLCD and AMOLED technology.

The hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used as switching device for large-area electronics such as active matrix liquid crystal displays (AM-LCDs). a-Si TFT is particularly advantageous to the production of large screen displays and facilitates mass production. When employing an a-Si:H layer, the main objectives are to enhance the field effect mobility and to reduce the off-state current under light illumination. The increase of field effect mobility results in wide application of a-Si:H TFTs in high resolution LCDs. On the other hand, a-Si:H has high photoconductivity which results in high off-state current of a-Si:H TFT under light illumination. The off-state leakage current under light illumination is, in particular, a serious problem in the projection and/or multimedia displays that require high intensity backlight illumination. Minimizing the off-current increase by a-Si photosensitivity is an important design consideration for achieving highimage-quality LCDs. TFT off-current increase by photoillumination of a-Si decreases the charge stored on the pixel during the TFT off-time, and results in gray-scale shading, flicker, crosstalk and other display nonuniformity in the LCD. The fluorine incorporated amorphous silicon [a-Si:H(:F)] and amorphous silicon (a-Si:H) were illuminated with backlight to investigate electrical characteristics. The effect of different [SiF4] / [ SiH4] ratio on the performance of a-Si:H(:F) TFTs was also studied. We found the density of states in the gap of a-Si:H(:F) will be modified by the introduction of F into a-Si:H and resulting the shift of the Fermi level toward the valence band edge. The density-of-states increasing cause more recombination centers for electrons and holes to increase the carrier recombination rate. The shift in the Fermi level leads to a reduction of the photoconductivity of a-Si:H(:F). Due to these two important factor, the photo leakage current decreases.

The off-state leakage current under back light illumination is, in particular, a serious problem in the multimedia displays that require high intensity backlight illumination. The photo leakage current characteristic of flexible a-Si:H TFTs has been measured in this study . The device activation energy (Ea) of a-Si:H TFTs extracted from various temperature measurements are different from those of typical a-Si:H TFTs, because the Fermi level of a-Si:H TFTs are modulate by the density of states (DOS) in the a-Si:H band gap. The information on DOS is important for understanding the physical mechanisms responsible for the device behavior. It¡¦s related to the threshold voltage,iii subthreshold slope, field effect mobility and the stability of the TFTs. Experimental results show the photo leakage currents of a-Si:H TFTs under tensile stress are less than that of flattened a-Si:H TFTs stemmed the weak light intensity. In addition, the small shifts of threshold voltage and subthreshold swing are resulted from the smaller Ea in a-Si:H channel material.

This thesis presents a high efficiency RF to DC converter for RFID applications. The proposed circuit has been designed in 90 nm CMOS technology using a single RF source. It exploits an internal Vth cancellation technique along with a leakage current reducer. The circuit operates in two phases: Phase 1, applies a DC voltage between gate and drain to reduce the VDS of the PMOS transistor; and Phase 2 removes this DC voltage meanwhile by pulling the drain and source terminals of the same transistor to the same potential, reducing the sub-threshold leakage current and enhancing the power conversion efficiency. The simulation results show that high DC power up to 8.1µA can be delivered to the load. The PCE has been measured 36.3% at -14.3dBm and can be improved to 54.5% providing an impedance matching network between the source and rectifier input.

Este trabalho apresenta os resultados obtidos em uma pesquisa, visando utilizar a corrente de fuga como parâmetro indicativo do estado de degradação de materiais poliméricos de rede compacta de média tensão, instalados em ambientes agressivos. Testes foram realizados em laboratório de modo a investigar o comportamento da corrente de fuga com o estado de degradação do material polimérico. Os resultados mostram que a corrente de fuga pode fornecer informações valiosas sobre a degradação. Uma análise minuciosa das características da corrente de fuga mostrou que a freqüência de ocorrência da razão terceira harmônica sobre a componente fundamental é a que melhor caracteriza o fenômeno da degradação. Novos testes foram realizados de forma a definir valores de referência para sua utilização como controle de campo para subsidiar a manutenção preventiva. Para o estado de atenção, foi estabelecida freqüência de ocorrência de 50 para a relação entre 0,35 e 0,40 para um período de 24 horas. Para o estado de alerta, foi estabelecida a freqüência de ocorrência de 80, para um período de 24 horas. Um equipamento foi construído e instalado para indicação no caso de ocorrência de trilhamento elétrico e erosão de materiais poliméricos de uma rede compacta instalada na orla marítima. / This paper presents results obtained after research, aiming at the utilisation of the leakage current to indicate the degradation of polymeric material of distribution line spacer and covered cables located in agressive enviroment. Tests were performed at the laboratory in order to investigate the behavior of the leakage current as function of the stage of degradation of polymeric material. The results showed that the leakage current can provide valuable information about the degradation. A closer analysis of the leakage current caracteristics revealed that the frequency of occurrence of the ratio of third harmonic to fundamental component is the the one that best characterize the degradation phenomenon. New analysis were carried out in order to define reference values to be used in the field, obtaining frequencie of occurrence of 50 and 80, for a ratio between 0,35 and 0,40, in a period of 24 hours, for the warning state and the preventive maintenance alert, respectively. A device was built and installed to indicate tracking and erosion of polymeric material in distribution lines located near the coast.

Este trabalho apresenta os resultados obtidos em uma pesquisa, visando utilizar a corrente de fuga como parâmetro indicativo do estado de degradação de materiais poliméricos de rede compacta de média tensão, instalados em ambientes agressivos. Testes foram realizados em laboratório de modo a investigar o comportamento da corrente de fuga com o estado de degradação do material polimérico. Os resultados mostram que a corrente de fuga pode fornecer informações valiosas sobre a degradação. Uma análise minuciosa das características da corrente de fuga mostrou que a freqüência de ocorrência da razão terceira harmônica sobre a componente fundamental é a que melhor caracteriza o fenômeno da degradação. Novos testes foram realizados de forma a definir valores de referência para sua utilização como controle de campo para subsidiar a manutenção preventiva. Para o estado de atenção, foi estabelecida freqüência de ocorrência de 50 para a relação entre 0,35 e 0,40 para um período de 24 horas. Para o estado de alerta, foi estabelecida a freqüência de ocorrência de 80, para um período de 24 horas. Um equipamento foi construído e instalado para indicação no caso de ocorrência de trilhamento elétrico e erosão de materiais poliméricos de uma rede compacta instalada na orla marítima. / This paper presents results obtained after research, aiming at the utilisation of the leakage current to indicate the degradation of polymeric material of distribution line spacer and covered cables located in agressive enviroment. Tests were performed at the laboratory in order to investigate the behavior of the leakage current as function of the stage of degradation of polymeric material. The results showed that the leakage current can provide valuable information about the degradation. A closer analysis of the leakage current caracteristics revealed that the frequency of occurrence of the ratio of third harmonic to fundamental component is the the one that best characterize the degradation phenomenon. New analysis were carried out in order to define reference values to be used in the field, obtaining frequencie of occurrence of 50 and 80, for a ratio between 0,35 and 0,40, in a period of 24 hours, for the warning state and the preventive maintenance alert, respectively. A device was built and installed to indicate tracking and erosion of polymeric material in distribution lines located near the coast.

In order to construct the integrated circuit with high efficiency, the size of the semiconductor devices becomes smaller and smaller. The surface of the chip is unable to offer enough area for devices interconnecting, that the Ultra Large Scale Integration (ULSI) has to adopt the construction of multilayer metal conductor line, and to decrease it¡¦s connects. However, the RC delay time becomes a main issue to limiting semiconductor speed when the electron signal was transferred between two metal connects. In order to solve the problem of RC delay, and to lower resistivity, copper (1.7 £g£[-cm) is applied instead of Aluminum (2.7 £g£[-cm) at present. In additation, to lower the capacitance, the low-k material has taken place SiO for reducing the electric capacity. In this work, the capacitance and current of MIM(Metal-Insulator-Metal) of interconnecting circuit were investigated under bending stress. SiOC of OSG (Organic silicate glass) layer has applied to a MIM structure. In order to apply the strain in devices, the device was bended to a fixed curvature for compressed and tensile stress. By bending the device, the capacitance and leakage current I-V & C-V were analyzed and compared with the unstressed SAMPLE of I-V and C-V at high temperature, too. The result reveals both of Schottky and Poole-Frenkel conduction mechanism existing in device under a high electric field of 1800 V/cm1/2, which indicates the theoretical treatment is unappropriate for the interpretation of the leakage current mechanism.