In order to construct the integrated circuit with high efficiency, the size of the semiconductor devices becomes smaller and smaller. The surface of the chip is unable to offer enough area for devices interconnecting, that the Ultra Large Scale Integration (ULSI) has to adopt the construction of multilayer metal conductor line, and to decrease it¡¦s connects. However, the RC delay time becomes a main issue to limiting semiconductor speed when the electron signal was transferred between two metal connects. In order to solve the problem of RC delay, and to lower resistivity, copper (1.7 £g£[-cm) is applied instead of Aluminum (2.7 £g£[-cm) at present. In additation, to lower the capacitance, the low-k material has taken place SiO for reducing the electric capacity. In this work, the capacitance and current of MIM(Metal-Insulator-Metal) of interconnecting circuit were investigated under bending stress. SiOC of OSG (Organic silicate glass) layer has applied to a MIM structure. In order to apply the strain in devices, the device was bended to a fixed curvature for compressed and tensile stress. By bending the device, the capacitance and leakage current I-V & C-V were analyzed and compared with the unstressed SAMPLE of I-V and C-V at high temperature, too. The result reveals both of Schottky and Poole-Frenkel conduction mechanism existing in device under a high electric field of 1800 V/cm1/2, which indicates the theoretical treatment is unappropriate for the interpretation of the leakage current mechanism.

With the digital systems moving towards higher frequencies, lower operating voltages and higher power, supplying the required current at the right voltage and at the right time to facilitate timely switching of the CMOS circuits becomes increasingly challenging. The board level power supply cannot meet these requirements directly due to the high inductance of the package interconnections. To overcome this problem, several thin film decoupling capacitors have to be placed on the IC or close to the IC in the package. Two approaches were pursued for high-k thin film decoupling capacitors. 1) Low cost sol-gel based thin film capacitors on organic board compatible Cu-foils 2) RF-sputtered thin film capacitors on silicon substrate for silicon compatible processes While sol-gel provides cost effective technology, sputtered ferroelectric devices are more compatible from manufacturing stand point with the existing technology. Nano-crystalline barium titanate and barium strontium titanate film capacitor devices were fabricated and characterized for organic and silicon substrates respectively. Sol-gel barium titanate films were fabricated first on a bare Cu-foil and then transferred to organic board through a standard lamination process. With process optimization and film doping, a capacitance density of 3 µF/cm2 was demonstrated with breakdown voltage greater than 12V. Leakage current characteristics, breakdown voltages, and electrical reliability of the devices were significantly improved through doping of the barium titanate films and modified film chemistry. Films and interfaces were characterized with high resolution electron microscopy, SEM, XRD, and DC leakage measurements. RF sputtering was selected for ferroelectric thin film integration on silicon substrate. Barium strontium titanate (BST) films were deposited on various electrodes sputtered on silicon substrates. The main focus was to improve interface stabilities for high-k thin films on Si to yield large-area defect-free devices. Effect of bottom electrode selection and barrier layers on device yield and performance were investigated carefully. High yield and high device performance was observed for certain electrode and barrier layer combination. A capacitance density up to 1 µF/cm2 was demonstrated with a breakdown voltage above 15 V on large area, 7 mm2, devices. These two techniques can potentially meet mid-high frequency future decoupling requirements.