Made available in DSpace on 2014-10-09T12:26:44Z (GMT). No. of bitstreams: 0 / Made available in DSpace on 2014-10-09T14:06:08Z (GMT). No. of bitstreams: 0 / Dissertacao (Mestrado) / IPEN/D / Instituto de Pesquisas Energeticas e Nucleares - IPEN-CNEN/SP

Made available in DSpace on 2014-10-09T12:26:44Z (GMT). No. of bitstreams: 0 / Made available in DSpace on 2014-10-09T14:06:08Z (GMT). No. of bitstreams: 0 / O câncer é hoje a segunda maior causa de morte por doenças em vários países, inclusive o Brasil. Excluindo-se o câncer de pele não melanoma, o câncer de próstata é o mais incidente na população, em geral. O tumor de próstata pode ser tratado por diversos métodos, incluindo a braquiterapia, que consiste na colocação de fontes radioativas seladas na forma de sementes, contendo o radioisótopo iodo-125 junto ao tumor. Dessa maneira, a região alvo do tratamento recebe alta dose de radiação, sendo essa dose reduzida sensivelmente nos tecidos circunvizinhos saudáveis. A semente é composta de uma cápsula de titânio selada por meio de soldagem, com 0,8mm de diâmetro externo e 4,5mm de comprimento, contendo em seu interior um fio de prata de 0,5mm de diâmetro, com o iodo-125 adsorvido. Após sua construção, a semente deve ser submetida a um ensaio de estanqueidade, garantindo a ausência de qualquer vazamento de material radioativo. Os principais objetivos deste trabalho foram o estudo e desenvolvimento dos métodos de ensaio de estanqueidade aplicáveis às sementes de iodo-125, propostos pela norma ISO 997820, a escolha do método mais adequado para o processo de produção e a determinação do fluxograma do processo a ser utilizado. Os ensaios realizados excederam a exigência da norma, com a aplicação de ultra-som durante o período de imersão das sementes. Os resultados mostraram a eficácia da aplicação de ultra-som, aumentando muito a detecção de vazamentos de material radioativo. Os melhores resultados foram obtidos utilizando-se água destilada a 20º C com imersão por 24 horas e água destilada a 70º com imersão por 30 minutos. Esses métodos são os escolhidos para serem utilizados durante a produção das sementes. O fluxograma de processo desenvolvido contempla todas as fases do ensaio de estanqueidade, de acordo com a seqüência realizada durante os experimentos. / Dissertacao (Mestrado) / IPEN/D / Instituto de Pesquisas Energeticas e Nucleares - IPEN-CNEN/SP

The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in this thesis: analytical modeling of behavioral level components for direct tunneling current and propagation delay, and the reduction of tunneling current during behavioral synthesis. Gate oxides of multiple thicknesses are useful in reducing the gate leakage dissipation. Analytical models from first principles to calculate the tunneling current and the propagation delay of behavioral level components is presented, which are backed by BSIM4/5 models and SPICE simulations. These components are characterized for 45 nm technology and an algorithm is provided for scheduling of datapath operations such that the overall tunneling current dissipation of a datapath circuit under design is minimal. It is observed that the oxide thickness that is being considered is very low it may not remain constant during the course of fabrication. Hence the algorithm takes process variation into consideration. Extensive experiments are conducted for various behavioral level benchmarks under various constraints and observed significant reductions, as high as 75.3% (with an average of 64.3%).

Polymer insulators are used in the power transmission and distribution industry as a good substitute to the porcelain and glass insulators. These polymer insulators have many advantages compared to porcelain insulators respectively. Significant improvement has been made in the performance of polymer insulators with continuous evaluation involving its performance and reliability under contaminated conditions for transmission and distribution purposes. This thesis investigates about the performance of polymer insulation under accelerated tracking and erosion test conditions conducted on distribution class polymer equipment’s like composite insulators and polymeric cutouts having a rated voltage of 15 kV. Further electrical tests, additional tests are done for investigating the dielectric strength of composite insulators and polymeric cutouts for studying its degradation process at macroscopic level.

京都大学 / 新制・課程博士 / 博士(工学) / 甲第24580号 / 工博第5086号 / 新制||工||1974(附属図書館) / 京都大学大学院工学研究科航空宇宙工学専攻 / (主査)教授 江利口 浩二, 教授 土屋 智由, 教授 平方 寛之 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

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As device technologies migrate into Deep Submicron (DSM) feature sizes, high-performance power-efficient computer architectures that keep pace with improving technologies need to be explored. Technology scaling increases the effects of wire latencies, inductive effects, noise and crosstalk in on-chip communication, limiting the performance of DSM designs. Power efficient performance gains from Instruction Level Parallelism (ILP) are reaching a limit. Single-Chip Parallel Computers are promising solutions to the DSM design challenges and the performance limitations of ILP. These systems are explicitly modular architectures that efficiently support Thread Level Parallelism (TLP) while avoiding global signals and shared resources. Microarchitectural level power analysis is required for evaluating the feasibility of newly conceived architectures in terms of power dissipation and energy efficiency. Accounting for power in the early stages of design shortens the time-to-market due to reduced design iteration times. Power optimizations at the architectural level can yield large power savings. This thesis proposes a microarchitectural level power estimation and analysis infrastructure for Single Chip Parallel Computers. The power estimation tool and the analysis methodology are developed based on the Single Chip Message-Passing Parallel (SCMP) Computer and can be extended to other Single Chip Parallel Computers. The thesis focuses on the development of power estimation models, construction of the power analysis tool, study of the power advantages of the architecture and identification of subsystems requiring power optimization. / Master of Science

Semiconductor lasers based on gallium arsenide and relatedmaterials are widely used in applications such as opticalcommunication systems, sensing, compact disc players, distancemeasurement, etc. The performance of these lasers can beimproved using a buried heterostructure offering lateralcarrier and optical confinement. In particular, if theconfinement (burying) layer is implemented by epitaxialregrowth of an appropriate aluminium-free semi-insulating (SI)material, passivation of etched surfaces, reduced tendency tooxidation, low capacitance and integration feasibility areadditional advantages. The major impediment in the fabrication of GaAs/AlGaAsburied-heterostructure lasers is the spontaneous oxidation ofaluminium on the etched walls of the structure. Al-oxide actsas a mask and makes the regrowth process extremely challenging.In this work, a HCl gas-basedin-situcleaning technique is employed successfully toremove Al-oxide prior to regrowth of SI-GaInP:Fe and SI-GaAs:Fearound Al-containing laser mesas by Hydride Vapour PhaseEpitaxy. Excellent regrowth interfaces, without voids, areobtained, even around AlAs layers. Consequences of usinginadequate cleaning treatments are also presented. Regrowthmorphology aspects are discussed in terms of different growthmechanisms. Time-resolved photoluminescence characterisation indicates auniform Fe trap distribution throughout the regrown GaInP:Fe.Scanning capacitance microscopy measurements demonstrate thesemi-insulating nature of the regrown GaInP:Fe layer. Thepresence of EL2 defects in regrown GaAs:Fe makes more difficultthe interpretation of the characterisation results in the nearvicinity of the laser mesa. GaAs/AlGaAs buried-heterostructure lasers, both in-planelasers and vertical-cavity surface-emitting lasers, withGaInP:Fe as burying layer are demonstrated for the first time.The lasers exhibit good performance demonstrating thatSI-GaInP:Fe is an appropriate material to be used for thispurpose and the suitability of our cleaning and regrowth methodfor the fabrication of this type of semiconductor lasers.Device characterisation indicates negligible leakage currentalong the etched mesa sidewalls confirming a smooth regrowthinterface. Nevertheless, experimental and simulation resultsreveal that a significant part of the injected current is lostas leakage through the burying material. This is attributed todouble carrier injection into the SI-GaInP:Fe layer.Simulations also predict that the function of GaInP:Fe ascurrent blocking layer should be markedly improved in the caseof GaAs-based longer wavelength lasers. <b>Keywords:</b>semiconductor lasers, in-plane lasers, VCSELs,GaAs, GaInP, semi-insulating materials, hydride vapour phaseepitaxy, regrowth, buried heterostructure, leakage current,simulation.

Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained systems. In addition, implementations of standard cryptographic methods can be prone to physical attacks that involve hardware level invasive or non-invasive attacks. Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent physical variation at the microscopic scale. Physical variation results from imperfection and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture variation in electrical characteristics to derive and establish a unique device-dependent challenge-response mapping. Prior to this work, PUF implementations were unsuitable for low power applications and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols for PUFs. To the best of our knowledge, this is the first comprehensive work that introduces and integrates these pieces together. The contributions include an introduction of structural requirements and metrics to classify and evaluate PUFs, design of novel architectures to fulfill these requirements, implementation and evaluation of the proposed architectures, and integration into real-world security protocols. First, I formally define and derive a new set of fundamental requirements and properties for PUFs. This work is the first attempt to provide structural requirements and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs. Second, using the proposed requirements, new and efficient PUF architectures are designed and implemented on both analog and digital platforms. In this work, the most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a population of FPGA devices. Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering and machine learning attacks. Using machine learning methods during the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication.

When multiple cold cathode fluorescent lamps (CCFLs) are set up in a backlight module, parasitic capacitances are inevitably existent between the lamps and the aluminum back-plank. These parasitic capacitances are different from each other in introducing different leakage currents, and in turn cause current imbalance between lamps with undesired unequal brightness of the backlight module. In order to tackle this current imbalance problem, it relies critically upon a balance driving scheme. This thesis adopts the impedance-matching principle for a uniform light output. A detailed analysis and design of the balance circuit is implemented in a direct-type backlight module, which employs a series resonant parallel-loaded inverter with a transformer to generate a high AC voltage to drive multiple lamps. Adding appropriate capacitors on the load resonant circuits helps alleviate the discrepancy among lamp currents. Based on the experimental results, the maximum total current deviation is defined as an index of the current imbalance for multiple lamps system. Accordingly, the minimum impedance ratio can be provided for the designers to achieve balance driving. A prototype of the multi-lamp driving circuit with balance capacitors is designed and built for a backlight module with 16 lamps in a 32-inch liquid crystal display (LCD). Simulation and experimental results demonstrate the effectiveness and feasibility of the current balance scheme.