Para manter o desempenho a uma tensão de alimentação reduzida, a tensão de threshold e as dimensões dos transistores têm sido reduzidas por décadas. A miniaturização do transistor para tecnologias sub-100nm resulta em um expressivo incremento nas correntes de fuga, tornando-as parte significativa da potencia total, alcançando em muitos casos 30-50% de toda a potencia dissipada em condições normais de operação. Por estas condições, correntes estáticas em células CMOS representam um importante desafio em tecnologias nanométricas, tornando-se um fator crítico no design de circuitos de baixa potência. Isto significa que dissipação de potência estática deve ser considerada o quanto antes no fluxo de projetos de circuitos integrados. Esta tese revisa os principais mecanismos de fuga e algumas técnicas de redução. Também é apresentado um modelo de estimativa rápida da corrente de subthreshold em células lógicas CMOS série - paralelo. Este método é baseado em associações de condutividade elétrica série – paralelo de transistores. Ao combinar com o modelo de estimativa da corrente de fuga de gate baseada nas condições estáticas dos transistores é possível fornecer uma melhor predição da corrente de fuga total em redes de transistores. O modelo de estimativa anterior é rápido porem seu foco não esta na precisão. Um novo e preciso modelo para corrente de fuga de subthreshold e de gate é também apresentado baseado em modelos analíticos simplificados das correntes de fuga. Ao contrario do modelo anterior que era destinado a redes de transistores serie – paralelo, o novo método avalia as correntes de fuga em rede de transistores complexas. A presença de transistores conduzindo em redes de transistores não conduzindo, ignorados em trabalhos anteriores, é também avaliado no trabalho proposto. O novo modelo de corrente de fuga foi validado através de simulações elétricas, considerando processos CMOS 130nm e 90nm, com boa correlação dos resultados, demonstrando a precisão do modelo. / To maintain performance at reduced power supply voltage, transistor threshold voltages and dimensions have been scaled down for decades. Scaling transistor into the sub-100nm technologies has resulted in a dramatic increase in leakage currents, which have become a significant portion of the total power consumption in scaled technologies, in many case achieving 30-50% of the overall power consumption under nominal operating conditions. For this condition, standby currents in CMOS logic gates represent an important challenge in nanometer technologies, leakage dissipation being a critical factor in low-power design. It means the static power dissipation should be considered as soon as possible in the integrated circuit design flow. This thesis reviews the major leakage current mechanisms and several reduction techniques. It presents the development of a straightforward method for very fast estimation of subthreshold current in CMOS series-parallel logic gates. This estimation method is based on electrical conductivity association of series-parallel transistor arrangements. Combined with a gate oxide leakage model based on transistor bias condition, it is possible to provide a better prediction of total leakage consumption in transistor networks. The previous estimation method is fast but it is not focused on accuracy. A new accurate subthreshold and gate leakage current estimation method is also developed based on simplified analytical leakage currents models. Instead of previous works focused on series-parallel device arrangements, this method evaluates the leakage in general transistor networks. The presence of on-switches in off-networks, ignored by previous works, is also considered in the proposed static current analysis. The new leakage model has been validated through electrical simulations, taking into account a 130nm and 90nm CMOS technology, with good correlation of the results, demonstrating the model accuracy.

Para manter o desempenho a uma tensão de alimentação reduzida, a tensão de threshold e as dimensões dos transistores têm sido reduzidas por décadas. A miniaturização do transistor para tecnologias sub-100nm resulta em um expressivo incremento nas correntes de fuga, tornando-as parte significativa da potencia total, alcançando em muitos casos 30-50% de toda a potencia dissipada em condições normais de operação. Por estas condições, correntes estáticas em células CMOS representam um importante desafio em tecnologias nanométricas, tornando-se um fator crítico no design de circuitos de baixa potência. Isto significa que dissipação de potência estática deve ser considerada o quanto antes no fluxo de projetos de circuitos integrados. Esta tese revisa os principais mecanismos de fuga e algumas técnicas de redução. Também é apresentado um modelo de estimativa rápida da corrente de subthreshold em células lógicas CMOS série - paralelo. Este método é baseado em associações de condutividade elétrica série – paralelo de transistores. Ao combinar com o modelo de estimativa da corrente de fuga de gate baseada nas condições estáticas dos transistores é possível fornecer uma melhor predição da corrente de fuga total em redes de transistores. O modelo de estimativa anterior é rápido porem seu foco não esta na precisão. Um novo e preciso modelo para corrente de fuga de subthreshold e de gate é também apresentado baseado em modelos analíticos simplificados das correntes de fuga. Ao contrario do modelo anterior que era destinado a redes de transistores serie – paralelo, o novo método avalia as correntes de fuga em rede de transistores complexas. A presença de transistores conduzindo em redes de transistores não conduzindo, ignorados em trabalhos anteriores, é também avaliado no trabalho proposto. O novo modelo de corrente de fuga foi validado através de simulações elétricas, considerando processos CMOS 130nm e 90nm, com boa correlação dos resultados, demonstrando a precisão do modelo. / To maintain performance at reduced power supply voltage, transistor threshold voltages and dimensions have been scaled down for decades. Scaling transistor into the sub-100nm technologies has resulted in a dramatic increase in leakage currents, which have become a significant portion of the total power consumption in scaled technologies, in many case achieving 30-50% of the overall power consumption under nominal operating conditions. For this condition, standby currents in CMOS logic gates represent an important challenge in nanometer technologies, leakage dissipation being a critical factor in low-power design. It means the static power dissipation should be considered as soon as possible in the integrated circuit design flow. This thesis reviews the major leakage current mechanisms and several reduction techniques. It presents the development of a straightforward method for very fast estimation of subthreshold current in CMOS series-parallel logic gates. This estimation method is based on electrical conductivity association of series-parallel transistor arrangements. Combined with a gate oxide leakage model based on transistor bias condition, it is possible to provide a better prediction of total leakage consumption in transistor networks. The previous estimation method is fast but it is not focused on accuracy. A new accurate subthreshold and gate leakage current estimation method is also developed based on simplified analytical leakage currents models. Instead of previous works focused on series-parallel device arrangements, this method evaluates the leakage in general transistor networks. The presence of on-switches in off-networks, ignored by previous works, is also considered in the proposed static current analysis. The new leakage model has been validated through electrical simulations, taking into account a 130nm and 90nm CMOS technology, with good correlation of the results, demonstrating the model accuracy.

Para manter o desempenho a uma tensão de alimentação reduzida, a tensão de threshold e as dimensões dos transistores têm sido reduzidas por décadas. A miniaturização do transistor para tecnologias sub-100nm resulta em um expressivo incremento nas correntes de fuga, tornando-as parte significativa da potencia total, alcançando em muitos casos 30-50% de toda a potencia dissipada em condições normais de operação. Por estas condições, correntes estáticas em células CMOS representam um importante desafio em tecnologias nanométricas, tornando-se um fator crítico no design de circuitos de baixa potência. Isto significa que dissipação de potência estática deve ser considerada o quanto antes no fluxo de projetos de circuitos integrados. Esta tese revisa os principais mecanismos de fuga e algumas técnicas de redução. Também é apresentado um modelo de estimativa rápida da corrente de subthreshold em células lógicas CMOS série - paralelo. Este método é baseado em associações de condutividade elétrica série – paralelo de transistores. Ao combinar com o modelo de estimativa da corrente de fuga de gate baseada nas condições estáticas dos transistores é possível fornecer uma melhor predição da corrente de fuga total em redes de transistores. O modelo de estimativa anterior é rápido porem seu foco não esta na precisão. Um novo e preciso modelo para corrente de fuga de subthreshold e de gate é também apresentado baseado em modelos analíticos simplificados das correntes de fuga. Ao contrario do modelo anterior que era destinado a redes de transistores serie – paralelo, o novo método avalia as correntes de fuga em rede de transistores complexas. A presença de transistores conduzindo em redes de transistores não conduzindo, ignorados em trabalhos anteriores, é também avaliado no trabalho proposto. O novo modelo de corrente de fuga foi validado através de simulações elétricas, considerando processos CMOS 130nm e 90nm, com boa correlação dos resultados, demonstrando a precisão do modelo. / To maintain performance at reduced power supply voltage, transistor threshold voltages and dimensions have been scaled down for decades. Scaling transistor into the sub-100nm technologies has resulted in a dramatic increase in leakage currents, which have become a significant portion of the total power consumption in scaled technologies, in many case achieving 30-50% of the overall power consumption under nominal operating conditions. For this condition, standby currents in CMOS logic gates represent an important challenge in nanometer technologies, leakage dissipation being a critical factor in low-power design. It means the static power dissipation should be considered as soon as possible in the integrated circuit design flow. This thesis reviews the major leakage current mechanisms and several reduction techniques. It presents the development of a straightforward method for very fast estimation of subthreshold current in CMOS series-parallel logic gates. This estimation method is based on electrical conductivity association of series-parallel transistor arrangements. Combined with a gate oxide leakage model based on transistor bias condition, it is possible to provide a better prediction of total leakage consumption in transistor networks. The previous estimation method is fast but it is not focused on accuracy. A new accurate subthreshold and gate leakage current estimation method is also developed based on simplified analytical leakage currents models. Instead of previous works focused on series-parallel device arrangements, this method evaluates the leakage in general transistor networks. The presence of on-switches in off-networks, ignored by previous works, is also considered in the proposed static current analysis. The new leakage model has been validated through electrical simulations, taking into account a 130nm and 90nm CMOS technology, with good correlation of the results, demonstrating the model accuracy.

The (BMN) bulk materials were sintered at 1050°C, 1100°C, 1150°C, 1200°C by the conventional ceramic process, and their microstructure and dielectric properties were investigated by Scanning electron microscopy (SEM), X-ray diffraction (XRD), Raman spectroscopy, Transmission electron microscopy (TEM) (including the X-ray energy dispersive spectrometry EDS and high resolution transmission electron microscopy HRTEM) and dielectric impedance analyzer. We systematically investigated the structure, dielectric properties and voltage tunable property of the ceramics prepared at different sintering temperatures. The XRD patterns demonstrated that the synthesized BMN solid solutions had cubic phase pyrochlore-type structure when sintered at 1050°C or higher, and the lattice parameter (a) of the unit cell in BMN solid solution was calculated to be about 10.56Å. The vibrational peaks observed in the Raman spectra of BMN solid solutions also confirmed the cubic phase pyrochlore-type structure of the synthesized BMN. According to the Scanning Electron Microscope (SEM) images, the grain size increased with increasing sintering temperature. Additionally, it was shown that the densities of the BMN ceramic tablets vary with sintering temperature. The calculated theoretical density for the BMN ceramic tablets sintered at different temperatures is about 6.7521 . The density of the respective measured tablets is usually amounting more than 91% and 5 approaching a maximum value of 96.5% for sintering temperature of 1150°C. The microstructure was investigated by using Scanning Transmission Electron Microscope (STEM), X-ray diffraction (XRD). Combined with the results obtained from the STEM and XRD, the impact of sintering temperature on the macroscopic and microscopic structure was discussed. The relative dielectric constant ( ) and dielectric loss ( ) of the BMN solid solutions were measured to be 161-200 and (at room temperature and 100Hz-1MHz), respectively. The BMN solid solutions have relative high dielectric constant and low dielectric loss. With increasing sintering temperature, the dielectric constant showed the maximum at 1150°C. The leakage current of BMN ceramic material is extraordinary small. When the voltage and thickness of the BMN capacitor are 4000V and 300um, the leakage current amounts only about 0.13-0.65 . The excellent physical and electrical properties make BMN thin films promising for potential tunable capacitor applications.

Indiana University-Purdue University Indianapolis (IUPUI) / Gopinath, Anoop. M.S.E.C.E., Purdue University, May 2018. Low-Power Hybrid TFET-CMOS Memory. Major Professor: Maher E. Rizkalla. The power consumption and the switching speed of the current CMOS technology have reached their limits. In contrast, architecture design within computer systems are continuously seeking more performance and e ciency. Advanced technologies that optimize the power consumption and switching speed may help deliver this e ciency. Indeed, beyond CMOS technology may be a viable approach to meeting the ever increasing need for low-power design. These technology includes devices such as Tunnel Field E ect Transistor (TFET), Graphene based devices such as GFET and GRNFET and FinFET. However, the low cross-sectional area of the channel asso- ciated with smaller technology nodes brings with it the challenges associated with leakage current below the threshold. Mitigating these challenges with devices such as TFETs may allow higher levels of integration, faster switching speed and lower power consumption. This thesis investigates the use of Gallium Nitride (GaN) TFET devices at 20nm for memory cells. These cells can be used in the L1 data cache of the Graphic Processing Units (GPU) thereby minimizing the static power and the dynamic power within these memory systems. The TFET technology was chosen since it has a low subthreshold slope of nearly 30mV/decade. This enables the TFET-based cells to function with a 0.6V supply voltage leading to reduced dynamic power consumption and leakage current when compared to the current CMOS technology. The results suggest that there are bene ts in pursuing an integrated TFET-based technology for Very Large Scale Integrated Circuit (VLSI) design. These bene ts are demonstrated using simulation at the schematic-level using Cadence Virtuoso.

With the MOSFET scaling practice, the performance of IC devices is improved tremendously as we experienced in the last decades. However, the small semiconductor devices also bring some drawbacks among which the high gate leakage current is becoming increasingly serious. This thesis work is focused on the of gate leakage current reduction in thin oxide semiconductor devices. The method being studied is the Phonon Energy Coupling Enhancement (PECE) effect induced by Rapid Thermal Processing (RTP). The basic MOS capacitors are used to check improvements of leakage current reduction after appropriate RTP process. Through sets of experiments, it is found that after RTP in Helium environment could bring about four orders reduction in gate leakage current of MOS capacitors.

Thesis (MScEng)--Stellenbosch University, 2012. / ENGLISH ABSTRACT: The use of high voltage direct current (HVDC) applications has gained enormous popularity for long distance power transmission. This is due to the lucrative benefits offered by this type of power transmission technology when compared to the traditional high voltage alternative current (HVAC). This new shift in the paradigm of power system design has led to the increased interest in the research that focuses on issues relating to the reliability of power supply associated with HVDC. Amongst such issues, insulation coordination has increasingly become a challenging task that continues to receive renewed research focus. It has been convincingly demonstrated, both from field experience and laboratory research, that insulator contamination constitutes a multifaceted phenomenon, especially when transmission voltages ramp up into high operating voltage levels. More so, this is particularly interesting with reference to the increasing applications of high voltage direct current (HVDC). The recently commissioned HVDC power-line in Namibia is one of the major motivations upon which NamPower (Namibia‟s national power utility) has committed financial resources to research on insulator pollution performance. This project was a part of NamPower‟s research initiative – seeking to investigate the phenomena associated with insulator pollution performance under natural pollution environments when energized under both AC and DC excitation voltage types. The significance of this research is especially crucial for HVDC applications given the paucity of research conducted on the DC performance of insulators, under natural pollution environments. This study was conducted at the Koeberg Insulator Pollution Test Station (KIPTS) on the west coast of Cape Town in the Western Cape province of South Africa. KIPTS is an internationally recognized insulator pollution test facility, which is widely used by both insulator manufacturers and academic researchers from many parts of the world. STRI and ABB, both Swedish-based companies, are good examples of international subscribers to the KIPTS research facility. The first objective of this research was to design a suitable DC excitation voltage system for both DC+ and DC- to be used at KIPTS. This apparatus was designed and built at the University of Stellenbosch. The second objective was to conduct a comparative evaluation of the performance of high temperature vulcanized silicone rubber (HTV-SR) power line insulators under AC, DC+ and DC- when subjected to natural pollution conditions at KIPTS. All test insulators were made from the same material and sourced from the same manufacturer – having different creepage lengths. Five different creepage lengths were considered for each excitation voltage – summing up to fifteen HTV-SR test samples. A standard DC glass disc insulator was also installed on each excitation voltage as a control sample. It was therefore envisaged that this study would give rise to new research questions, leading to future explorations on the subject. With reference to weather monitoring and leakage current measurements (using an online leakage current monitoring device - OLCA), a correlation was found to exist between the variations in climatic conditions and the corresponding occurrence of leakage current on the insulator surfaces. High leakage current levels were recorded in summer due to the high pollution levels that were measured in that season (using the equivalent salt deposit density (ESDD) approach). Winter, in contrast, had lower levels of leakage current recorded. This corresponds to a high prevalence of rainfall in winter, which caused occasional natural washing of the insulator surfaces. The leakage current levels for the HTV-SR insulators were of a similar order of magnitude for AC and DC+ and lower for DC-. The harshest pollutants (with high conductivities, as measured with the directional dust deposit gauges (DDDG)) were found to have emanated largely from the south. As a result, most instances of erosion were observed in the southward direction on the test insulators. The electrical discharge activity observations, conducted at night, had revealed that dryband corona (DBC) and dryband discharge (DBD) prominently occurred on the terminating sheaths (both live and ground ends) and bottom side of HTV-SR and glass disc insulators, respectively. This justifies the dominance of erosion that was observed on the terminating sheaths and bottom side of HTV-SR and glass disc insulators, respectively. Flashover events were recorded on the shortest HTV-SR insulator installed on DC+ and the glass disc insulator installed on DC-. All flashover events occurred in summer (the harshest season at KIPTS). Two interesting observations, albeit unexplained, were observed: star-shaped erosion on the shed bottoms of the HTV-SR insulators installed on DC+ and material peel-off at the shed-to-sheath bonding interface of the HTV-SR insulators installed on DC-. These observations therefore require further investigation in order to establish possible explanations. / AFRIKAANSE OPSOMMING: Die gebruik van hoë gelykspanning (HSGS) het baie gewild geword vir kragtransmissie oor lang afstande. Dit is as gevolg van die uitstekende voordele wat hierdie tipe tegnologie teenoor die tradisionele hoë wisselspanning (HSWS) bied. Hierdie paradigmaskuif in die ontwerp van kragstelsels het tot verhoogde belangstelling in navorsing gelei wat betrekking het op aspekte wat verband hou met die betroubaarheid van kragvoorsiening deur HSGS. Van hierdie aspekte word isolasiekoördinasie toenemend ʼn uitdagende taak en navorsing word tans daarop toegespits. Daar bestaan oortuigende bewyse, gebaseer op laboratorium- en veldtoetse dat isolatorbesoedeling ʼn verskynsel met vele fasette is, veral wanneer hoër spannings gebruik word. Dit is in „n meerdere mate van belang met verwysing na toepassings van HSGS. Die onlangs inbedryfgestelde HSGS kraglyn in Namibië is een van die hoofmotiverings vir die verskaffing van geldelike steun deur NamPower (Namibië se nasionale kragvoorsiener) vir navorsing oor die besoedelingsprestasie van isolators. Hierdie projek is deel van NamPower se navorsingsinisiatief om verskynsels betreffende die besoedelingsprestasie van isolators in natuurlik-besoedelde omgewings te ondersoek, onder WS en GS-bekragtiging. Die betekenis van hierdie navorsing is veral belangrik vir die HSGS-toepassings in die lig van die skaarsheid van navorsing oor die GS-prestasie van isolators in natuurlik-besoedelde omgewings. Hierdie studie is gedoen by die Koeberg isolatorbesoedelingstoetsstasie (KIPTS) aan die weskus van die Wes-Kaap. KIPTS is 'n internasionaal-erkende toetsfasiliteit en word algemeen gebruik deur beide isolatorvervaardigers en akademiese navorsers uit baie dele van die wêreld. STRI en ABB, albei Sweeds-gebaseerde maatskappye, is die goeie voorbeelde van die internasionale gebruikers van die KIPTS navorsingsfasiliteit. Die oogmerk van hierdie navorsing was om eerstens 'n geskikte GS-kragbron vir beide die GS+ en die GS- vir gebruik by KIPTS te ontwerp. Hierdie apparaat is ontwerp en gebou deur die Universiteit van Stellenbosch. Tweedens is 'n vergelykende evaluering van die prestasie hoë temperatuur gevulkaniseerde silikoon (HTV-SR) kraglynisolators onder WS, GS+ en GS– onder natuurlike besoedeling by die KIPTS uitgevoer. Alle toetsisolators is van dieselfde materiaal gemaak en is afkomstig van dieselfde vervaardiger, maar het verskillende kruipafstande. Vyf verskillende kruipafstande is gebruik vir elke tipe spanning  'n totaal van vyftien HTV-SR toets monsters. 'n Standaard GS glasisolatorskyf is ook vir elke spanning as' n kontrolemonster geïnstalleer. Dit kan dus verwag word dat hierdie studie aanleiding sal gee tot nuwe navorsingsvrae, wat kan lei tot verdere toekomstige ondersoeke oor die onderwerp. Met verwysing na die monitering van die weer en die lekstroommetings (met behulp van 'n aanlyn-lekstroommoniteringstoestel - OLCA), is 'n korrelasie gevind tussen die variasie in klimaatstoestande en die ooreenstemmende voorkoms van lekstroom op die isolator- oppervlaktes. Hoë lekstroomvlakke is waargeneem in die somer, as gevolg van die hoë besoedelingsvlakke wat in daardie seisoen gemeet is (met behulp van die ekwivalente soutneerslag-digtheid (ESDD) metode). In die winter, in teenstelling, is die laagste vlakke van lekstroom aangeteken. Dit stem ooreen met 'n hoë voorkoms van reënval in die winter, wat die isolatoroppervlaktes van tyd tot tyd natuurlik gewas het. Die lekstroomvlakke op die HTV-SR isolators was van soortgelyke ordegrootte vir WS en GS+ maar laer vir GS-. Dit is bevind dat die ergste besoedelingstowwe, met 'n hoë geleiding, soos gemeet met die rigtingsensitiewe stofneerslagsmeters (DDDG), hoofsaaklik uit ʼn suidelike rigting kom. As gevolg hiervan, is die meeste gevalle van erosie aan die suidekant van die toetsisolators waargeneem. Die waarneming van elektriese ontladingsaktiwiteit in die nag, het aan die lig gebring dat droëbandkorona (DBC) en droëbandontladings (DBD) prominent voorgekom het op die skedes aan die uiteindes (beide lewende en grond kante) en onderste kant van HTV-SR en glasskywe, onderskeidelik. Oorvonkings is waargeneem op die kortste HTV-SR isolator op GS+ en op die glasisolator op GS-. Al die oorvonkings het in die somer (die ergste seisoen by KIPTS) voorgekom. Twee interessante, dog onverklaarbare, verskynsels is waargeneem: stervormige erosie aan die onderkante van die skerms van die HTV-SR isolators op GS+ en material-afskilfering by die skerm-skede tussenvlak van die HTV-SR isolators op GS-. Hierdie verskynsels vereis verdere ondersoek ten einde moontlike verklarings vas te stel.

Silicon Oxide/Oxynitride (SiO2/SiON) has been the mainstream material used for gate dielectric for MOS transistors for the past 30 years. The aggressive scaling of the feature size of MOS transistor has limited the ability of SiO2/SiON to work effectively as the gate dielectric to modulate the conduction of current of MOS transistors due to excess leakage current dominated by direct quantum tunneling. Due to this constraint, alternative gate dielectric/high-k is being employed to reduce the leakage current in order to maintain the rate of scaling of MOS transistors. However, the cost involved in the implementation of these new gate dielectric materials are high due to the requirements of a change in the process flow for device fabrication. This work presents the results of a novel processing method implementing the use of rapid thermal processing (RTP) on conventional SiO2/SiON gate dielectric to reduce the gate leakage current by three to five orders of magnitude. Electrical properties of the effect were characterized on fabricated MOS capacitors using semiconductor parameter analyzer and LCR meter. Material characterization was performed using FT-IR to understand the mechanism involved in this novel processing method, named PECE (Phonon-Energy-Coupling-Enhancement). By implementing this novel process, the use of SiO2/SiON as gate dielectric can be scaled further in conventional process flow of device fabrication.

Introduction: Haemodialysis (HD) is a treatment in which blood from the patient is lead through a tubing system into a dialysis device in a extracorporeal circuit. This circuit contains semipermeable membranes (dialyzer). Blood with uraemic toxins flows on one side, and a salt solution flows on the other side. The salt solution flushes away waste products that have passed the membrane by diffusion or convection through small pores. From there the blood returns to the patient through a tubing system that contains an air-trap and a sensor to avoid air contamination in the blood. Besides air contamination, this treatment is burdened with safety problems such as biocompatibility, electrical safety and mechanical safety. The aim of this thesis was to investigate the safety issues in haemodialysis devices regarding leakage current and air contamination during standard procedures and simulated fault conditions. Does the dialysis device constitute a risk for the patient? Methods: To determine the extent of leakage current in HD machines, measurements at the filter-coupling site were performed in vitro according to the safety standard, IEC 601-1, in 5 types of dialysis machines. To determine, in vitro, to what extent blood and priming fluid allowed leakage current to pass to the patient, leakage current were also measured in the blood lines. The blood line was filled with blood from donors or priming fluid in eight different runs. To determine if leakage current could influence biocompatibility, a Fresenius 2008C dialysis machine and 8 hemophan dialyzers were used. Blood lines contained about 400 ml heparinized blood from each of 8 different donors (in vitro). C3d was measured, in vitro, before start of a simulated dialysis and at 15, 30, 45 and 60 min. during standard dialysis procedure. Then 1.5 mA current was switched on and additional samples were drawn at 75 and 90 min. Some patients need a central dialysis catheter (CDC) for access, placed close to or within the heart. To analyze if leakage current during standard HD would influence the ECG, patients with CDC or with AV-fistula as access were investigated. To analyse if air contamination could occur without activating security alarms in the dialysis device, various modes of in vitro dialysis settings were studied, some using a dextran solution to mimic blood viscosity. Besides visual inspection an ultrasound detector for microemboli and microbubbles was also used. Results: The data showed leakage current at the filter coupling site that was significantly higher for some devices than for others. The leakage current could pass through blood and priming fluid. It exceeded the cardiac floating (CF)-safety limit (<50μA) at the top of the CDC using the test mains on applied part for saline (median 1008μA), for blood (median 610μA) and for a single fault condition using saline (median 68 μA) or blood (47 μA). The leakage current experiments showed that complement activation worsened as the leakage current increased. During standard dialysis arrhythmia could occur. Microbubbles were visible at the bottom of the air-trap and bubbles could pass the air-trap towards the venous line without triggering the alarm. During recirculation, several ml of air could be collected in an intermediate bag after the venous line. Ultrasound showed the presence of bubbles of sizes 2.5-50 μm as well as more than 50 μm silently passing to the venous line in all runs performed. In conclusion, the data showed that a leakage current in HD devices can be high enough to be a safety risk for the patient. This risk is greater if a single fault arises in the dialysis machine or another device connected to the same patient, or during mains contact to the patient. Then the current flow may be high enough to cause arrhythmia for the patient, especially when using a CDC. There is also reason for concern that micro bubble transmission may occur without inducing an alarm. These factors need to be looked over to improve safety regulations and optimize HD treatment and service schedules.

En esta tesis se han desarrollado modelos compactos de corriente de fuga por túnel de puerta en SOI MOSFET (de simple y doble puerta) avanzados basados en una aproximación WKB de la probabilidad de túnel. Se han estudiado los materiales dieléctricos high-k más prometedores para los diferentes requisitos de nodos tecnológicos de acuerdo ala hoja de ruta ITRS de miniaturización de dispositivos electrónicos. Hemos presentado un modelo compacto de particionamiento de la corriente de fuga de puerta para un MOSFET nanométrico de doble puerta (DG MOSFET), utilizando modelos analíticos de la corriente de fuga por el túnel directo de puerta. Se desarrollaron también Los modelos analíticos dependientes de la temperatura de la corriente de túnel en la región de inversión y de la corriente túnel asistido por trampas en régimen subumbral. Finalmente, se desarrolló una técnica de extracción automática de parámetros de nuestro modelo compacto en DG MOSFET incluyendo efectos de canal corto. La corriente de la puerta por túnel directo y asistido por trampas modelada mediante los parámetros extraídos se verificó exitosamente mediante comparación con medidas experimentales.