In switched-mode power supplies (SMPS), a Controller is required for output voltage or current regulation. In low-power SMPS, processing power from a fraction of watt to several hundred watts, digital implementations of the controller, i.e. digital controllers have recently emerged as alternatives to the predominately used analog
systems. This is mostly due to the better design portability, power management capability, and the potential for implementing advanced control techniques, which are not easy to realize with analog
hardware.
However, the existing digital implementations are barely functional replicas of analog designs, having comparable dynamic performance if not poorer. Due to stringent constraints on hardware requirements, the digital systems have not been able to demonstrate some of their most attractive features, such as parameter estimation, controller auto-tuning, and nonlinear time-optimal control for improved transient response.
This thesis presents two novel digital controllers and systems. The first is an auto-tuning controller that can be implemented with simple hardware and is suitable for IC integration.
The controller estimates power stage parameters, such as output capacitance, load resistance, corner frequency and damping factor by examining the amplitude and frequency of intentionally introduced
limit cycle oscillations. Accordingly, a digital PID compensator is automatically redesigned and the power stage is adapted to provide good dynamic response and high power processing efficiency. Compared to state of the art analog solutions, the controller has similar bandwidth and improves overall efficiency.
To break the control bandwidth limitation associated with the sampling effects of PWM controllers, the second part of the thesis
develops a nonlinear dual-mode controller. In steady state, the controller behaves as a conventional PWM controller, and during
transients it utilizes a continuous-time digital signal processor (CT-DSP) to achieve time-optimal response. The processor performs a capacitor charge balance based algorithm to achieve voltage recovery
through a single on-off sequence of the power switches. Load transient response with minimal achievable voltage deviation and a
recovery time approaching physical limitations of a given power stage is obtained experimentally.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/11284 |
| Date | 01 August 2008 |
| Creators | Zhao, Zhenyu |
| Contributors | Prodic, Aleksandar |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
| Format | 5169012 bytes, application/pdf |
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