We proposes an efficient algorithm for extracting SPICE-compatible circuits of embedded interconnect structures from FDTD-simulated time-domain reflections. A layer-peeling technique (LPT) is used to obtain the time-domain step response of the interconnects under extract (IUE) itself. A pencil matrix method is then used to get the pole-residue representation of the time-domain step response of the IUE. A pole-reducing procedure is implemented based on a bandwidth criterion to simplify pole-residue representation. Finally, the lumped equivalent models of the IUE are synthesized by an equivalent lumped-model extraction technique, in which four types of equivalent model bases are used. The equivalent circuit can be easily implemented in SPICE-like simulator. Several transmission line structures are presented as examples to demonstrate the validity of the proposed algorithm both in time and frequency domains.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0624102-205937 |
| Date | 24 June 2002 |
| Creators | Chang, Hsiao-Chen |
| Contributors | Tzong-Lin Wu, Huey-Ru Chuang, Tzyy-Sheng Horng, Chin-Wen Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0624102-205937 |
| Rights | off_campus_withheld, Copyright information available at source archive |
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