The effect of electromigration on void formation and the failure mechanism of FCBGA packages under a current density of 1*104 A/cm2 and an environmental temperature of 150¢J was investigated. Eight solder/substrate combinations of four lead-free solder systems with two substrates were examined to verify the failure modes. A conservative failure criterion was adopted to define and predict the failure of the package. SEM was employed to observe in situ microstructural changes, IMC growth, and failure modes.
All samples exhibited a similar failure, attributed mainly to void occupation along UBM/solder interfaces at the cathode chip side of the bumps with downward electron flow. Voids were initiated at the corner due to current crowding. Two specific void locations were identified at the IMC/solder and UBM/IMC interfaces, and they co-existed in the same specimen but in different bumps. No void coupling mode was found. Since the atom diffusion rate in the solder differs from that in the IMC layer, the voids can be formed between them. A current density of 1*104 A/cm2 was sufficiently high to form a void pattern at the IMC/solder interface. However, the formation of voids at the UBM/IMC interface is generally induced by the consumption of UBM, since the high temperature of 150¢J crucially dominates the void morphology at the UBM/IMC interface. The difference among solder systems did not affect the failure modes nor dominate mechanisms. Two theoretical models based on the experimental results were applied to describe the void formations. They will be more accurate and useful in understanding void formations by further experimental data provided.
According to the results of solder bumps with electrons only flowed through Al trace line at die side, it suggested that atoms transport toward the bottom substrate along with the temperature gradient and toward the right corners along with electron flow when electrons flowed through the trace after the resistances of solder joints reaching 120¢H of their initial values.
With respect to the differences of substrate surface finishes, more voids appeared at the cathode substrate side of the solders combined with Cu/Ni/Au pad than those combined with Cu-OSP after long-term upward electron stressing. It suggested another possible failure at the substrate side when failure did not occur at the chip side in an EM test.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0706109-124801 |
| Date | 06 July 2009 |
| Creators | Liu, Lee-cheng |
| Contributors | Yi-Shao Lai, Chi-Hui Chien, Chorng-Fuh Liu, J.C.Huang, Huang-Kuang Kung, Rong-Sheng Chen, Tei-Chen Chen, Ming Chen, Jao-Hwa Kuang, Ming-Hwa R. Jen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-124801 |
| Rights | unrestricted, Copyright information available at source archive |
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