The effect of electromigration on void formation and the failure mechanism of FCBGA packages under a current density of 1*104 A/cm2 and an environmental temperature of 150¢J was investigated. Eight solder/substrate combinations of four lead-free solder systems with two substrates were examined to verify the failure modes. A conservative failure criterion was adopted to define and predict the failure of the package. SEM was employed to observe in situ microstructural changes, IMC growth, and failure modes. All samples exhibited a similar failure, attributed mainly to void occupation along UBM/solder interfaces at the cathode chip side of the bumps with downward electron flow. Voids were initiated at the corner due to current crowding. Two specific void locations were identified at the IMC/solder and UBM/IMC interfaces, and they co-existed in the same specimen but in different bumps. No void coupling mode was found. Since the atom diffusion rate in the solder differs from that in the IMC layer, the voids can be formed between them. A current density of 1*104 A/cm2 was sufficiently high to form a void pattern at the IMC/solder interface. However, the formation of voids at the UBM/IMC interface is generally induced by the consumption of UBM, since the high temperature of 150¢J crucially dominates the void morphology at the UBM/IMC interface. The difference among solder systems did not affect the failure modes nor dominate mechanisms. Two theoretical models based on the experimental results were applied to describe the void formations. They will be more accurate and useful in understanding void formations by further experimental data provided. According to the results of solder bumps with electrons only flowed through Al trace line at die side, it suggested that atoms transport toward the bottom substrate along with the temperature gradient and toward the right corners along with electron flow when electrons flowed through the trace after the resistances of solder joints reaching 120¢H of their initial values. With respect to the differences of substrate surface finishes, more voids appeared at the cathode substrate side of the solders combined with Cu/Ni/Au pad than those combined with Cu-OSP after long-term upward electron stressing. It suggested another possible failure at the substrate side when failure did not occur at the chip side in an EM test.

Avec les avancées technologiques et la miniaturisation, le réseau d'interconnexions est devenu de plus en plus dense et complexe. Pour les domaines qui utilisent des applications à forts courants, comme l'automobile, les très fortes densités de courant dans les lignes métalliques peuvent conduire à des phénomènes comme l'électromigration, le voltage drop ou encore les surcharges électriques. La conception des circuits doit donc être réalisée en prenant en compte ces contraintes et en adaptant la largeur des lignes aux courants. Ce travail de thèse a eu comme objectif de développer des solutions pour la prise en compte des contraintes en courant lors de la phase de routage de blocs analogiques fort courants. Après une présentation des phénomènes impliqués et de l'état de l'art, une approche algorithmique pour l'aide au routage est introduite. Une méthode de caractérisation du courant est définie, un algorithme exhaustif de routage est présenté, puis utilisé pour effectuer des recherches de critères d'une bonne topologie. Deux algorithmes sont ensuite étudiés et comparés, un algorithme glouton, servant de référence, et un « Divide & Conquer » original. Il présente une amélioration d'environ 10% pour l'aire, et presque 27% en temps CPU par rapport à l'algorithme glouton. La section suivante s'intéresse à la correction du current crowding, avec une méthode basée sur un ensemble de modèles mathématiques. Enfin, un flot basé sur les solutions développées durant la thèse est présenté et validé. / In deep submicron VLSI circuits, excessive current density in interconnects is a major concern for analog high current application. If current over maximum density is not effectively mitigated, this can lead to phenomena like electromigration, voltage drop and electrical overload. It is a hot topic of interest in modern circuits due to the decrease of metal track sizes while high currents are necessary in automotive or mobile applications. This thesis had as goal to develop solutions for the consideration of the constraints in the current phase of routing analog blocks strong currents. After a presentation of the phenomena and the state of the art, an algorithmic approach to current driven net generation is introduced. A method to characterize the current is defined. Then an exhaustive routing algorithm is presented and used to search criteria for a good topology. Next, two algorithms are studied and compared, first a greedy algorithm, used as a reference, and a "Divide & Conquer" original algorithm. It shows results improved on average by about 10% for area and almost 27% for CPU time compared with existing solution. The next section focuses on current crowding correction, with a method based on a set of mathematical models. Finally, a conception flow based on the developed solutions is introduced and validated.

Core-shell nanowire LEDs are light emitting devices which, due to a high aspect ratio, have low substrate sensitivity, allowing the possibility of low defect density GaN light emitting diodes. Current growth techniques and physical non-idealities make the production of high conductivity p-type GaN for the shell region of these devices difficult. Due to the structure of core-shell nanowires and the difference in conductivity between ntype and p-type GaN, the full junction area of a core-shell nanowire is not used efficiently. To address this problem, a series of possible doping profiles are applied to the core of a simulated device to determine effects on current crowding and overall device efficiency. With a simplified model it is shown that current crowding has a possible dependence on the doping in the core in regions other than those directly in contact with the shell. The device efficiency is found to be improved through the use of non-constant doping profiles in the core region with particularly large efficiency increases related to profiles which modify portions of the core not in contact with the shell

Superconducting Nanowire Single Photon Detectors (SNSPDs) are a promising technology for detecting single photon emissions with high efficiency and low noise. This detector class has numerous applications in quantum optics, communication, and sensing. One typical design for these devices is the hairpin structure, in which a superconducting nanowire is patterned into a meandering shape. The combination of academic research and interest from the industry is boosting the development of hairpin SNSPD devices to achieve high detection efficiency while maintaining fast response time and low jitter, requiring optimization of the device geometry, materials properties, and sophisticated readout electronics. This thesis qualitatively enquires about different device geometries, varying turn designs and features. Moreover, proposing a promising experimental setup with the potential of being scaled up to simultaneously test numerous devices with a varying magnetic field, driving the hairpin SNSPDs to their detection limit, and enabling further quantitative studies to deepen the understanding of the underlying mechanisms currently hindering the SNSPDs. Analyzing the acquired data draws results regarding the critical current and dark counts trends. Furthermore, at low magnetic field strength, the enquired devices are found to have their critical current enhanced. Moreover, comparisons are drawn among similar design structures. Furthermore, a discussion on manufacturing defects detrimental to the SNSPD performance is initiated. Finally, further studies on this topic adopting the presented method are encouraged to acquire additional quantitative results to be compared with theoretical models describing the thin superconducting structures. / Superconducting Nanowire Single Photon Detectors (SNSPD) är en lovande teknik för att detektera utsläpp av enstaka fotoner med hög effektivitet och lågt brus. Denna detektorkategori har många tillämpningar inom kvantoptik, kommunikation och avkänning. En typisk konstruktion för dessa anordningar är hairpin-strukturen, där en supraledande nanotråd är mönstrad i en slingrande form. Kombinationen av akademisk forskning och intresse från industrin ökar utvecklingen av hairpin-SNSPD-enheter för att uppnå hög detektionseffektivitet med bibehållen snabb responstid och låg jitter, vilket kräver optimering av enhetens geometri, materialegenskaper och sofistikerad avläsningselektronik. I denna avhandling undersöks kvalitativt olika anordningsgeometrier, varierande vridningsdesign och funktioner. Dessutom föreslås en lovande experimentell uppställning med potential att skalas upp för att samtidigt testa många anordningar med ett varierande magnetfält, vilket driver hairpin-SNSPD:erna till sin detektionsgräns och möjliggör ytterligare kvantitativa studier för att fördjupa förståelsen av de underliggande mekanismer som för närvarande hindrar SNSPD:erna. Analysen av de insamlade uppgifterna ger resultat när det gäller den kritiska strömmen och trenderna för mörkertalet. Dessutom visar sig de undersökta enheterna ha en ökad kritisk strömstyrka vid låg magnetfältsstyrka. Dessutom görs jämförelser mellan liknande konstruktionsstrukturer. Dessutom inleds en diskussion om tillverkningsfel som är skadliga för SNSPD:s prestanda. Slutligen uppmuntras ytterligare studier i detta ämne med den presenterade metoden för att få ytterligare kvantitativa resultat som kan jämföras med teoretiska modeller som beskriver tunna supraledande strukturer.

General lighting with InGaN light emitting diodes (LEDs) as light sources is of particular interest in terms of energy savings and related environmental benefits due to high lighting efficiency, long lifetime, and Hg-free nature. Incandescent and fluorescent light sources are used for general lighting almost everywhere. But their lighting efficiency is very limited: only 20-30 lm/W for incandescent lighting bulb, approximately 100 lm/W for fluorescent lighting. State-of-the-art InGaN LEDs with a luminous efficacy of over 200 lm/W at room temperature have been reported. However, the goal of replacing the incandescent and fluorescent lights with InGaN LEDs is still elusive since their lighting efficiency decreases substantially when the injection current increases beyond certain values (typically 10-50 Acm-2). In order to improve the electroluminescence (EL) performance at high currents for InGaN LEDs, two approaches have been undertaken in this thesis. First, we explored the preparation and characterization of non-polar and semi-polar GaN substrates (including a-plane, m-plane and semi-polar planes). These substrates serve as promising alternatives to the commonly used c-plane, with the benefit of a reduced polarization-induced electric field and therefore higher quantum efficiency. It is demonstrated that LEDs on m-plane GaN substrates have inherently higher EL quantum efficiency and better efficiency retention ability at high injection currents than their c-plane counterparts. Secondly, from a device structure level, we explored the possible origins of the EL efficiency degradation at high currents in InGaN LEDs and investigated the effect of hot electrons on EL of LEDs by varying the barrier height of electron blocking layer. A first-order theoretical model is proposed to explain the effect of electron overflow caused by hot electron transport across the LED active region on LED EL performance. The calculation results are in agreement with experimental observations. Furthermore, a novel structure called a “staircase electron injector” (SEI) is demonstrated to effectively thermalize hot electrons, thereby reducing the reduction of EL efficiency due to electron overflow. The SEI features several InyGa1-yN layers, with their In fraction (y) increasing in a stepwise manner, starting with a low value at the first step near the junction with n-GaN.