This thesis includes two topics. The first topic is a high speed phase adjustable ROM-less DDFS (Direct Digital Frequency Synthesizer). The second one is a low-power SRAM design.
The high speed phase adjustable ROM-less DDFS employs trigonometric quadruple angle formula with the adjustability of phase and frequency. Neither any scaling tables nor error correction tables are required. In order to meet demands of general communication systems, the ROM-less DDFS is aimed at generating the frequencies for IQ channels. A pipelining design is adopted in our design to boost the frequency of the DDFS.
The low-power SRAM uses a negative word-line scheme to reduce the leakage current of word-line controlled transistors (WCT). The leakage current increases with the high density of SRAM which might cause reading and writing errors. The negative word-line scheme not only reduces the leakage current as well as the power, but also makes the SRAM operate reliably during read and write cycles.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0710104-220316 |
| Date | 10 July 2004 |
| Creators | Lin, Wun-Ji |
| Contributors | Jih-Ching Chiu, Sying-Jyan Wang, Chua-Chin Wang, Ing-Jer Huang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-220316 |
| Rights | unrestricted, Copyright information available at source archive |
Page generated in 0.0019 seconds