The constant matrix multiplication is one of the key operations in many applications including digital signal processing, communication, and coding. In general, constant matrix multiplication can be expressed as bit-level Boolean functions. Then, common subexpression elimination (CSE) can be used to reduce the area cost of realizing these bit-level functions by finding the shared common factors among these bit-level equations. The proposed circuit generator performs logic reduction on the input Boolean functions and produces the simplified Verilog HDL codes as output. Then the simplified code is fed into Synopsys Design Compiler for further logic minimization and technology mapping to generate gate-level netlists. In this thesis, we present ten different CSE algorithms for logic reduction of the bit-level Boolean functions. The comparisons include both the architecture-level technology-independent results and the Synopsys synthesized technology-dependent results. According to the experiments, we observe that our CSE can effectively reduce the area cost. We also apply the CSE to the design of the Advanced Encryption Standard (AES) in cryptography.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0725105-125204 |
| Date | 25 July 2005 |
| Creators | Lin, Chi-Cheng |
| Contributors | Shiann-Rong Kuang, Ko-Chi Kuo, Ming-Der Shieh, Jih-Ching Chiu, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725105-125204 |
| Rights | off_campus_withheld, Copyright information available at source archive |
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