Univ., Diss.--Bochum, 2006. / Enth. Zsfassung in engl. und dt. Sprache.

The constant matrix multiplication is one of the key operations in many applications including digital signal processing, communication, and coding. In general, constant matrix multiplication can be expressed as bit-level Boolean functions. Then, common subexpression elimination (CSE) can be used to reduce the area cost of realizing these bit-level functions by finding the shared common factors among these bit-level equations. The proposed circuit generator performs logic reduction on the input Boolean functions and produces the simplified Verilog HDL codes as output. Then the simplified code is fed into Synopsys Design Compiler for further logic minimization and technology mapping to generate gate-level netlists. In this thesis, we present ten different CSE algorithms for logic reduction of the bit-level Boolean functions. The comparisons include both the architecture-level technology-independent results and the Synopsys synthesized technology-dependent results. According to the experiments, we observe that our CSE can effectively reduce the area cost. We also apply the CSE to the design of the Advanced Encryption Standard (AES) in cryptography.

Zugl.: Zürich, Techn. Hochsch., Diss., 2006 / Auch im Internet unter der Adresse http://e-collection.ethbib.ethz.ch/ecol-pool/diss/fulltext/eth16351.pdf verfügbar

Most process of lease is done manually in the past. Since the networks were used extensively and systems of Point of Sales risen quickly, the efficiency of administration of payment flow had been obviously promoted. What are mostly encrypted are information of payment flow, but what we encrypt is the information of leased products this time. We apply encryption technique to the lease system, and access information via RS-232 devices, such as SmartCard Reader and EM Reader. After processing of system and encryption, the system will transfer the processed data to the server. In this paper, we take Kaohsiung C-Bike Lease System for case study, our discussion will focus on network packet, data encryption, and real-time monitoring. We will also introduce critical features and mechanisms of the lease system and address some issues we encountered. This system encrypts data via Advanced Encryption Standard, sends out data packets via TCP/IP, and monitors leased bikes via databases and framework of multi-thread.

We live in an age where we willingly provide our social security number, credit card information, home address and countless other sensitive information over the Internet. Whether you are buying a phone case from Amazon, sending in an on-line job application, or logging into your on-line bank account, you trust that the sensitive data you enter is secure. As our technology and computing power become more sophisticated, so do the tools used by potential hackers to our information. In this paper, the underlying mathematics within ciphers will be looked at to understand the security of modern ciphers. An extremely important algorithm in today's practice is the Advanced Encryption Standard (AES), which is used by our very own National Security Agency (NSA) for data up to TOP SECRET. Another frequently used cipher is the RSA cryptosystem. Its security is based on the concept of prime factorization, and the fact that it is a hard problem to prime factorize huge numbers, numbers on the scale of 2^{2048} or larger. Cryptanalysis, the study of breaking ciphers, will also be studied in this paper. Understanding effective attacks leads to understanding the construction of these very secure ciphers.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

With the development of Internet, there are more and more applications around us are connected tightly with it. Security of network is important. This thesis will follow OSI 7-layers architecture, which defined by ISO, to propose several hardware improvement approaches of network security. In data-link layer, we improve performance of CRC calculation with parallel CRC calculation, such that a 32-bit data can be finished using CRC calculation in one cycle. In network layer and transport layer, bit-oriented instruction set has good performance for processing packet header. In application, we implement DES and AES algorithm in hardware. We integrate all hardware module with ARM7TDMI coprocessor¡¦s interface. Finally, we download integrated circuit into Xilinx XCV2000E chip to observe its demo to verify it.

Στη σύγχρονη ζωή του ανθρώπου η ανταλλαγή και η διακίνηση της πληροφορίας αποτελεί πλέον αναπόσπαστο κομμάτι. Η τεράστια ανάπτυξη των δικτύων υπολογιστών και η επικοινωνία πληροφοριών κάθε μορφής έφερε ένα τεράστιο πρόβλημα στην επιφάνεια, την ανάγκη για προστασία αυτής της πληροφορίας. Το πρόβλημα αυτό καλείται να το αντιμετωπίσει η επιστήμη της Κρυπτογραφίας όπου μέσα από διάφορους μετασχηματισμούς προσπαθεί θα μετατρέψει τα δεδομένα σε μια ακατανόητη μορφή η οποία θα είναι δυνατόν να αντιστραφεί μόνο από τον νόμιμο παραλήπτη. Για το λόγο αυτό έχουν αναπτυχθεί πληθώρα αλγορίθμων κρυπτογράφησης όπου παρόλο που η δουλειά τους είναι η ίδια, χειρίζονται και μετασχηματίζουν τα δεδομένα με διαφορετικό τρόπο. Στην παρούσα εργασία γίνεται παρουσίαση του αλγορίθμου AES (Advanced Encryption Standard) που αποτελεί το τρέχον πρότυπο από το NIST (National Institute of Standards and Technology). Ο AES ο οποίος είναι και γνωστός ως Rijndael, είναι ένας συμμετρικός αλγόριθμος τμήματος και βασίζεται στα δίκτυα μετάθεσης – αντικατάστασης, ενώ είναι υλοποιήσιμος και γρήγορος τόσο σε λογισμικό όσο και σε υλικό. Αντίθετα με τον προκάτοχο του DES, δεν χρησιμοποιεί το δίκτυο Feistel. Εφαρμόζεται σε έναν πίνακα Bytes 4x4 (128 bits), που ορίζεται ως κατάσταση (state), με τους περισσότερους μετασχηματισμούς να πραγματοποιούνται σε ένα πεπερασμένο πεδίο. Ο αλγόριθμος AES, δίνει τη δυνατότητα κρυπτογράφησης με τρία κλειδιά διαφορετικού μήκους, 128 bits κλειδί με 10 κύκλους επανάληψης, 192 bits κλειδί με 12 κύκλους επανάληψης και 256 bits κλειδί με 14 κύκλους επανάληψης παρουσιάζοντας κάθε φορά μεγάλη ανθεκτικότητα σε κρυπταναλυτικές επιθέσεις.Στα πλαίσια της εργασίας έγινε λεπτομερής ανάλυση των μετασχηματισμών που χρησιμοποιεί ο AES στην κρυπτογράφηση και αποκρυπτογράφηση σύμφωνα με το πρότυπο Fips-197 αρχικά σε θεωρητικό επίπεδο και έπειτα πραγματοποιήθηκαν υλοποιήσεις σε λογισμικό και σε υλικό. Συγκεκριμένα, στο 1ο κεφάλαιο της εργασίας γίνεται μια εισαγωγή στην Κρυπτογραφία, παρουσιάζοντας τις βασικές της έννοιες και την ιστορική της εξέλιξη από τα πρώτα χρόνια εμφάνισης της ως σήμερα. Στο κεφάλαιο 2, αρχικά παρουσιάζονται τα υπάρχοντα κρυπτοσυστήματα, αναδεικνύοντας κάθε φορά τον τρόπο με τον οποίο λειτουργούν, τους αλγόριθμους που υπάγονται σε αυτά και τις εφαρμογές που έχουν. Στη συνέχεια γίνεται σύγκριση μεταξύ των αλγορίθμων ενός συστήματος αλλά και μεταξύ των κρυπτοσυστημάτων. Το κεφάλαιο 3 αποτελεί το κυρίως σώμα της εργασίας καθώς σε αυτό παρουσιάζεται και επεξηγείται ο αλγόριθμος AES. Δίνεται το απαραίτητο μαθηματικό υπόβαθρο και αναλύονται οι μετασχηματισμοί του αλγορίθμου. Παρουσιάζεται ο τρόπος που επεκτείνονται τα κλειδιά του αλγορίθμου καθώς και οι διαδικασίες κρυπτογράφησης και αποκρυπτογράφησης. Τέλος γίνεται αναφορά σε ζητήματα ασφάλειας και στην αντοχή του AES σε κρυπταναλυτικές επιθέσεις, καθώς και στις εφαρμογές που χρησιμοποιείται. Στο 4ο κεφάλαιο παρουσιάζονται και συγκρίνονται οι μέθοδοι υλοποίησης του αλγορίθμου. Περιγράφεται μια υλοποίηση σε λογισμικό με τη χρήση της γλώσσας προγραμματισμού C++, η οποία επεκτείνεται και σε μια διαδικτυακή υλοποίηση και μια υλοποίηση σε υλικό με τη χρήση της περιγραφικής γλώσσας VHDL και το σχεδιαστικό εργαλείο Quartus II. Τέλος στο 5ο κεφάλαιο εξάγονται συμπεράσματα και γίνονται προτάσεις για μελλοντική εργασία. / In modern life the exchange and transfer of information has become an integral part. The enormous development of computer networks and the information communication of every form, has brought a new massive problem on the surface, the need to protect this information.The science of Cryptography is challenged to face this problem, so through various transformations is trying to convert tha data in a incomprehensive form, which will be possible to be inverted only from the legal receiver. For this reason a variety of algorithms have been developed and although their work is the same, they handle and convert data in different ways. In the present thesis the AES (Advanced Encryption Standard) algorithm is presented, which is the current standard of NIST (National Institute of Standards and Technology). AES, which is also known as Rijndael, is a symmetric block cipher and is based on substitution - permutation networks, while it can be efficiently implemented both in software and hardware. Unlike it's predecessor DES, it does not use Feistel network. It is applied in 4x4 Bytes matrix (128 bits), which is defined as state, with the most transformations to be performed in a finite field. AES algorithm provides encryption capability with three keys of different size: key of 128 bits with 10 rounds, key of 192 bits with 12 rounds and key of 256 bits with 14 rounds. This thesis includes detailed analysis of transformations that AES uses in ecryption and decryption according to the Fips-197 standard, along with software and hardware implementations. Specifically, in the first chapter an introduction to Cryptography is made, presenting basic concepts and a historical overview. In chapter 2, contemporary cryptosystems are introduced. In chapter 3 the AES algorithm is presented and explained. The necessary mathematical background is provided and the transformations of the algorithm are analysed. The way the algorithm keys are expanded is presented, as well as the encryption and decryption processes. In chapter 4 the implementations of AES are presented and compared. An implementation in software is described using the programming language C++, and an implementation in hardware is given using the VHDL language and the design tool Altera Quartus II. Finally in chapter 5 the conclusions are given and proposals are made for future work.

This work is focused on cipher algorithm AES, his selection method and description of cipher blocks, possibilities of .NET framework and current implementation of AES algorithm in C#. The book also contain complete application for teaching and explanation of AES cipher.