In deep submicron region, scaling the sizes of devices and chips down is indispensable. The silicide at ultra-shallow extension area is used in order to keep low sheet resistance while junction depth is scaled. To introduce the implant between source and channel keeps high saturation current. Furthermore, we put two blocks of oxide between source and channel to suppress the short channel effect, which are able to resist depletions. We also demonstrate the capacitor-less memory cell. We use the variation of the charge and bias replacing the real capacitor. The device is promising candidate for reduced chip size.
According to the simulation results of ISE TCAD, the device with silicide at ultra-shallow extension area and the implantation between source and channel provide higher saturation current. The MOS with block oxide has high Ion/Ioff and low DIBL. We simulate different materials, different high and width of the block oxide, and discuss the effects of those device¡¦ characteristics. We show two methods of the implantation which can improve the charge density of pseudo neutral region. Those three structures provide an solution to make device and chip be scaled down easily.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0728104-232310 |
| Date | 28 July 2004 |
| Creators | Ming, Chih |
| Contributors | Chia Hsiung Kao, Yao Tsung Tsai, Jyi Tsong Lin, Shyh Jye Joe |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728104-232310 |
| Rights | not_available, Copyright information available at source archive |
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