Hannover, Universiẗat, Diss., 2004.

ABSTRACT In this work , a Four-Point probe electrical measurement system has been set up to investigate the non-linear conductivity of gold thin film on silicon . The annealing effect of gold thin films has been carried out by a rapid thermal annealing system using a modified tube furnace .The conductivities of gold thin film on silicon are studied for film thickness of 100-500 Å , different annealing temperature from 150-500¢J, annealing duration of 10-40mins on two kinds of substrate¡]n-type¡Bp-type silicon¡^. Samples are examined by SEM¡BAFM¡BXRD and FTIR to characterize the surface morphology of gold thin film on silicon , the silicide formation,and non-linear dc response in every different conditions. Finally , we proposed a Random Tunneling Junction Network model to explain the non-linear dc response and discussed the correlation between the tunneling junction of gold clusters and the changes of it¡¦s distribution , the silicide formation combining with breakdown of the junction bridges and the parameters from the RTJN model. Our numerical result reveals good agreement with the experiment data.

Düsseldorf, Universiẗat, Diss., 2000.

No description available.

In deep submicron region, scaling the sizes of devices and chips down is indispensable. The silicide at ultra-shallow extension area is used in order to keep low sheet resistance while junction depth is scaled. To introduce the implant between source and channel keeps high saturation current. Furthermore, we put two blocks of oxide between source and channel to suppress the short channel effect, which are able to resist depletions. We also demonstrate the capacitor-less memory cell. We use the variation of the charge and bias replacing the real capacitor. The device is promising candidate for reduced chip size. According to the simulation results of ISE TCAD, the device with silicide at ultra-shallow extension area and the implantation between source and channel provide higher saturation current. The MOS with block oxide has high Ion/Ioff and low DIBL. We simulate different materials, different high and width of the block oxide, and discuss the effects of those device¡¦ characteristics. We show two methods of the implantation which can improve the charge density of pseudo neutral region. Those three structures provide an solution to make device and chip be scaled down easily.

The Integral Inherently Safe Light Water Reactor (I2S-LWR) is a novel reactor concept which aims to apply safety-promoting features typical of small modular reactors (SMRs) to a large pressurized water reactor (PWR) of 3000 MWt, thus providing an option for a passively safe reactor to markets which would find greater economic benefit in a large reactor. Pushing the compact core of an integral reactor to 3000 MWt necessitates several design innovations to remain within safety margins while meeting the goal of increased power density. The I2S-LWR fuel assembly takes on a 19x19 lattice with reduced fuel rod dimensions relative to traditional Westinghouse-type 17x17 PWR fuel assemblies. It is anticipated that the I2S-LWR will eventually employ uranium silicide (U3Si2) fuel instead of uranium oxide (UO2) to improve thermal performance. These unique design features are closely tied to the I2S-LWR core neutronics, thereby necessitating a thorough investigation of reactivity control options. This thesis considers the design of both control rods and burnable absorbers on the basis of the I2S-LWR uranium silicide fuel assembly. Fuel assembly designs are considered with various control rod arrangements and burnable absorber layouts with several candidate absorber materials and concentrations. Viable fuel assembly designs must meet targets for reactivity and power peaking while satisfying constraints on core safety and cycle length. Designs are developed in a heuristic manner, and key performance metrics are processed at each iteration. Characteristics of common optimization algorithms are mimicked at a high level so as to guide the progression of design iterations. The optimized fuel assembly designs produced in this way are recommended for use in core loading pattern design.

No description available.

3D VLSI with a CoolCube TM process allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. The thermal budget allowed to process the top transistor is currently limited by NiPt silicide stability of the bottom transistor. To extend the upper transistors thermal process window, Pre-Amorphization Implant (PAI) and Si-Capping were used to improve the stability of NiPt 15% on SiC:P and SiGe 30% :B accesses. While PAI enhances the silicide stability on SiC:P substrate from 600°C 2h to 700°C 2h, neither PAI nor Si-Capping improve silicide stability on SiGe 30% :B. To provide a solution for P accesses stability, NiCo 10% silicidation has been developed. Combined with PAI and Si-Capping, the germano-silicide offers a higher stability (up to 600°C 2h) than its NiPtSi 15% counterpart.

Chemnitz, Techn. Univ., Diplomarb., 2002.

An curvature measurement technique was used to characterize the stress evolution during reaction of a Ni film and a silicon substrate to form nickel silicide. Stress changes were measured at each stage of the silicide growth. When the nickel films were subjected to long-time isothermal annealing, stresses that developed during silicide formation gradually relaxed. Fitting the experimental results with a kinetic model provides insight into the volumetric strain and relaxation behavior of the reacting film and the reaction product. / Singapore-MIT Alliance (SMA)