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System level power estimation for power manageable System-on-chip

The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means that it needs more power consumption. Therefore, the essential issue that we are facing now is to reduce the power consumption in order to fit the capacity of the batteries. In the current system level design, there is no presentable commercial tool for designers to estimate the power consumption of the system. This thesis proposes a framework for system level power estimation, which allows the users to add the power models of these modules developed by them in the system level. Moreover, the power models of CPU, memory and bus are also provided. Besides the power models and convenient method to modify these models, a power management unit is also provided. With this unit, the designers can use different power management policies to manage the system¡¦s power consumption and decide its power efficiency. In this thesis, the framework is constructed under the environment of SystemC, so the users can alternate the power model and power management policy rapidly. By using this framework, the designers can more conveniently and rapidly estimate the system¡¦s power consumption and improve the system¡¦s architecture. Therefore, it can fast examine the advantages and disadvantages of various power models and power management policies.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0805109-102151
Date05 August 2009
CreatorsChou, Hung-I
ContributorsChung-Ho Chen, Shiann-Rong Kuang, Jer-Min Jou, Shen-Fu Hsiao, Pei-Yin Chen
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151
Rightsunrestricted, Copyright information available at source archive

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