This thesis is composed of three parts. The first part surveys the literature on RF architecture and semiconductor process technology in the DVB-H tuner applications. The RFIC design considerations are also discussed. In the second part, the DVB-H tuner RFIC design using TSMC 0.18£gm RF CMOS technology is presented. Discussions between simulated and measured results of each circuit stage are also included. In the third part, the RFIC testing results for CW and DVB-H input signals are demonstrated. For a QPSK signal with 8MHz bandwidth and 7/8 code rate, the sensitivity of the RFIC can reach -87dBm. The adjacent channel protection ratio can meet the specification. The chip power consumption is 70.2mW, and the chip size is 1.96 mm2.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0816107-183121 |
| Date | 16 August 2007 |
| Creators | Lian, Yi-jie |
| Contributors | Huey-Ru Chuang, Kang-Chun Peng, Tzong-Lin Wu, Tzyy-Sheng Horng, Sheng-Fuh Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0816107-183121 |
| Rights | unrestricted, Copyright information available at source archive |
Page generated in 0.0018 seconds