In the design of the recently embedded processor, besides paying attention to low power consumption and reducing the complexity of the design, it is also necessary to be with high performance. Because of the advanced logic CMOS technology, incorporated multiple processor cores on a single chip becomes the new trend which improve performance. This thesis, being designed for the embedded processor, presents a superscalar dual core architecture for ARM9 ISA. The processor provides three operation modes: single-core mode, superscalar mode, and multithreading mode for designer. The processor can be switched dynamically in three mode with the new extended instructions, when it is executing the program. When the processor is executing in superscalar mode, the designer can use the processor without changing any setting of the original environment. According our simulation result, the superscalar dual core architecture can obtain 52% performance speedup when it execute the trace of MPEG2 decoder and obtain average 41% performance speedup comparing to the five-stage pipelined ARM9 architecture.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0821105-231417 |
| Date | 21 August 2005 |
| Creators | Chou, Yu-Liang |
| Contributors | Ing-Jer Huang, Jih-Ching Chiu, Tsung Lee, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0821105-231417 |
| Rights | withheld, Copyright information available at source archive |
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