In this thesis, an efficiency method for reducing the rotation ROM size in table-based architecture is proposed. The original rotation can be divided into two stages, coarse stage and fine stage. Our approach modifies the previous two-stage rotation method and proposes a multi-stage architecture and discuses three-stage phase calculation. The effect of table reduction is more apparently for higher accuracy requirement in the three-stage architecture. The total area of the previous two-stage architecture is larger than the proposed table-reduced three-stage architecture because the table size takes a significant ratio of the total area especially when the required bit accuracy is large. In the proposed three-stage design, there are two different types of architectures, depending on the rotation angles in the first and second rotation stages. Comparison of different types of architecture with the previous method shows that our designs indeed reduce the table size and the total area significantly.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0901109-043220 |
| Date | 01 September 2009 |
| Creators | Cheng, Yen-Chun |
| Contributors | Chung-Ho Chen, Shen-Fu Hsiao, Shiann-Rong Kuang, Jih-ching Chiu, Pei-Yin Chen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901109-043220 |
| Rights | unrestricted, Copyright information available at source archive |
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