In the System-on-Chip (SoC) era, common industry estimates are that functional verification takes approximately 70% of the total effort on a project. For the time-to-market constrain, it¡¦s a challenge to reduce the SoC verification/debugging time efficiently. In an SoC, a microprocessor is an essential part of it. First, we focus the debugging problem on microprocessors. An in-circuit emulation (ICE) module that can be embedded with a microprocessor core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typical debugging and testing mechanisms, including boundary scan paths, partial scan paths, single stepping, internal resource monitoring and modification, breakpoint detection, and mode switching between debugging and normal modes. The architecture of the ICE module is parameterized and retargetable to different microprocessors. It has been successfully integrated with two microprocessors with significantly different architectures: one 8-bit industrial embedded microcontroller HT48x00 and one 32-bit ARM7-like embedded microprocessor. FPGA prototypes and chip implementation have been accomplished. Experiments show that real-time (on-line) debugging at full speed is possible with the embedded ICE at a minor gate count overhead.
Collecting the program execution traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real time program traces are so huge such that real-time program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress program execution traces in real time in order to reduce the trace size. The approach consists of three modularized phases: (1) branch/target filtering, (2) branch/target address encoding and (3) Lempel-Ziv-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1K to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1).
For SoC debugging, bus signal tracing represents that the information which is generated from the system can be collected for later observation, debugging and analysis. However, the generation rate and the size of real time system traces are so huge such that a mechanism for system tracing that can reduce trace size efficiently is needed. In this paper, we propose a multi-resolution bus trace approach. The hardware bus tracer consists of two major stages: (1) signal monitor & tracing stage, and (2) trace compression stage. In the first stage, designer can trace the signals in detail or in rough depends on the debug purpose. In other word, the multi-resolution trace approach provides the trade-off between trace accuracy and trace depth. In the second stage, the bus tracer compresses the trace size efficiently; therefore the capability of on-chip storage is increased. In the host, the analyzer tool decompresses the trace data for future observation and debugging.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0910107-093301 |
| Date | 10 September 2007 |
| Creators | Kao, Chung-fu |
| Contributors | Jin-Hua Hong, Tian-Sheuan Chang, Juinn-Dar Huang, Chia-Lin Yang, Ing-Jer Huang, Jing-Yang Jou |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910107-093301 |
| Rights | not_available, Copyright information available at source archive |
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