Return to search

Integration of VHDL simulation and test verification into a Process Model Graph design environment /

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 116-117). Also available via the Internet.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/31059192
Date January 1994
CreatorsDailey, David M.,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceThis resource online

Page generated in 0.0017 seconds