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Integration of VHDL simulation and test verification into a Process Model Graph design environment /Dailey, David M., January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 116-117). Also available via the Internet.
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A framework for synthesis from VHDL /Shah, Sandeep R., January 1991 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaves 91-94). Also available via the Internet.
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Behavior modeling of RF systems with VHDL /Sama, Anil, January 1991 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaf 107). Also available via the Internet.
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Rapid development of VHDL behavioral models /Wright, Philip A., January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.
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A hierarchical approach to effective test generation for VHDL behavioral models /Rao, Sanat R., January 1993 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 147-149). Also available via the Internet.
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The semantics of VHDL with VAL and HOL towards practical verification tools /Van Tassel, John P. January 1900 (has links)
Thesis (M.A.)--Wright State University, 1990. / Cover title. "June 1990." Includes bibliographical references.
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Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistantVan Tassel, John Peter January 1993 (has links)
No description available.
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Formal methods for VLSI designRead, Simon January 1994 (has links)
No description available.
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VHDL modeling and simulation of a digital image synthesizer for countering ISAR /Kantemir, Ozkan. January 2003 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Douglas J. Fouts, Phillip E. Pace. Includes bibliographical references (p. 143-144). Also available online.
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Automatic verification of VHDL models /Ardeishar, Raghu, January 1990 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Vita. Abstract. Includes bibliographical references (leaves 74-75). Also available via the Internet.
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