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A parametrized CAD tool for VHDL model development with X Windows /Singh, Balraj, January 1990 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Vita. Abstract. Includes bibliographical references (leaves 52-54). Also available via the Internet.
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Assertion-checker synthesis for hardware verification, in-circuit debugging and on-line monitoringBoulé, Marc. January 1900 (has links)
Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2008/05/09). Includes bibliographical references.
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Optimization techniques for distributed Verilog simulationLi, Lijun, January 1900 (has links)
Thesis (Ph.D.). / Written for the School of Computer Science. Title from title page of PDF (viewed 2008/02/12). Includes bibliographical references.
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Aspects of hardware methodologies for the NTRU public-key cryptosystem /Wilhelm, Kyle. January 2008 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (p. 69-72).
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Hazard detection with VHDL in combinational logic circuits with fixed delays /Chu, Ming-Cheung, January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 181-182). Also available via the Internet.
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Representation and simulation of a high level language using VHDL /Edwards, Carleen Marie, January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.
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VHDL modeling and design of an asynchronous version of the MIPS R3000 microprocessor /Fanelli, Paul. January 1994 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1994. / Typescript. Includes bibliographical references (leaves 124-125).
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Behavioral delay fault modeling and test generation /Joshi, Anand Mukund, January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 165-169). Also available via the Internet.
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Efficient VHDL models for various PLD architectures /Giannopoulos, Vassilis. January 1995 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Bibliography: leaf 55.
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Natural language interface to a VHDL modeling tool /Manek, Meenakshi. January 1993 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 79-80). Also available via the Internet.
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