Report (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 60-62). Also available via the Internet.

Lab-on-a-Chip systems and the associated micro-fabrication technologies have been around for almost three decades. However, the rapidly shifting technological landscape and the multidisciplinary nature of the engineering know-how have made it extremely difficult for a majority of these technologies to materialize to find applications and find commercial products. In order to address this gap, researchers worldwide have attempted to implement design automation paradigms typically used for VLSI engineering and apply them to these Lab-on-a-Chip. However, almost all of these efforts have been disconnected, resulting in a delayed/stalled application of algorithmic advances on real-world device design. FluigiCAD will allow the rapid application and integration of innovative ideas into a single cohesive workflow. / 2024-06-13T00:00:00Z

This thesis describes the design and implementation of a hardware synthesis system based on design descriptions provided in VHDL. Several aspects of the synthesis problem are examined. These include the design of an internal format to represent multiple levels of design information, algorithms for synthesis, optimizations, and verification of the synthesis process. Key features of this system include the ability to synthesize models that span a wide range of design description abstraction levels. The synthesis system internal format contains data structures for algorithmic, dataflow, as well as structural VHDL constructs. This framework for performing synthesis over a wide range of abstraction levels is the novel feature of this system. Optimizations for register-transfer level (dataflow) models are discussed along with their implementation. The design and implementation of the synthesis library, which contains information about the hardware components available to perform the synthesis, is also discussed. The output of the synthesis system is in the form of two files, an RNL format netlist and a purely structural VHDL netlist. In order to produce the actual hardware layout, the RNL netlist must be input to VPNR, a standard cell place and route system. The structural VHDL may be simulated to verify the synthesis process. Results of mixed level synthesis are provided. / Master of Science

This thesis describes the development of the Hierarchical Behavioral Test Generator (HBTG) for the testing of VHDL behavioral models. HBTG uses the Process Model Graph of the VHDL behavioral model as the base for test generation. Test sets for individual processes of the model are precomputed and stored in the design library. Using this information, HBTG hierarchically constructs a test sequence that tests the functionality of the model. The test sequence generated by HBTG is used for the simulation of the model. Various features present in HBTG and the implementation of the algorithm are discussed. The idea of an effective test sequence for a VHDL behavioral model is proposed. A system is presented to evaluate the quality of the test sequence generated by the algorithm. Test sequences and coverage results are given for several models. Some suggestions for future improvements to the tools are made. The HBTG forms part of a complete CAD system for rapid development and testing of VHDL behavioral models. / Master of Science

The enhancement of a CAD tool called Modeler's Assistant is discussed. This tool allows VHDL behavioral models to be developed more rapidly than with traditional techniques. The limitations present in the previous version of the tool (Version 2) are discussed. The correction of these limitations and the enhancement of Modeler's Assistant are the focus of the work described in this thesis. New features present in the enhanced version of Modeler's Assistant (Version 3) include the ability to create and maintain a library of parameterized process primitives and the ability to graphically represent hierarchy in VHDL behavioral models through the use of supernodes. Other enhancements that allow more features of the VHDL language to be used in Modeler's Assistant are described. Several examples that illustrate the use of these enhanced features are presented. / Master of Science

Behavioral modeling of RF systems with VHDL is considered and a modeling methodology is developed for modeling the I/O response of these systems. A Pulsed Doppler radar system is chosen as a representative system, and a VHDL model for this system is presented. The modeling approach and the working of the model are explained, and some example runs are provided. Some problems that are posed by VHDL in attempting to model the behavior of RF systems are discussed, along with the solutions that we adopted. A fault diagnosis methodology for systems of this type that uses information about the behavior of the system (extracted from a VHDL model of the system) is discussed, and an example is presented. / Master of Science

Several technologies are being made available for the blind and the visually impaired with the use of infrared and sonar sensors, Radio Frequency Identification, GPS, Wi-Fi among others. Current technologies utilizing microprocessors increase the device's power consumption. In this project, a Verilog Hardware Language (VHDL) designed handheld device that autonomously guides a visually impaired user through an obstacle free path is proposed. The goal is to minimize power consumption by not using the usual microcontroller and replacing it with components that can increase its speed. Utilizing six infrared sensors, the handheld device is modeled after current technologies which use IR and sonar sensors which are reviewed in this project. By using behavioral modeling, an algorithm for obstacle avoidance and the generation of the obstacle free path is reduced using a K-map and implemented using a multiplexer. / by Ernesto Cividanes. / Thesis (M.S.C.S.)--Florida Atlantic University, 2010. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2010. Mode of access: World Wide Web.

This thesis discusses the ability to maintain a consistent design, simulation, and test verification environment by use of the Process Model Graph (PMG) throughout the development process. This ability extends the functionality of the PMG to include the visualization of simulation results and the verification of test paths within the simulation. These ideas have been implemented within a development tool called the Modeler's Assistant. The integration of the test generation environment into the tool is discussed. The design methodology used in creating the simulation environment is also discussed. Other enhancements to increase the abilities of the tool and improve its usefulness to behavioral test generation and verification are also discussed. Many examples of the new extentions to the tool are presented. / Master of Science

This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data path synthesis and control unit synthesis. The conversion of data path synthesis is done in this thesis. In the DIADES system a digital system is described on the behavioral level in terms of variables and operations using the language ADL. The digital system described in ADL is compiled to a format called GRAPH language. In the GRAPH language the behavior of a digital system is represented by a specific sequence of program statements. The descriptions in the GRAPH language is compiled to a format called STRU CT language. The system is described in the STRU CT language in terms of lists of nodes and arrows. The main task of this thesis is to convert the descriptions in the GRAPH language and the descriptions in the STRUCT language to the VHDL format. All the generated VHDL Code will be Mentor Graphics VHDL format compatible, and all the VHDL code can be compiled, simulated and synthesised by the Mentor Graphics tools.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990. / Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.