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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
11

Simulation of large-scale system-level models /

Chadha, Vikrampal, January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 95-98). Also available via the Internet.
12

Process level test generation for VHDL behavioral models /

Kapoor, Shekhar, January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 126-128). Also available via the Internet.
13

Development of VHDL behavioral models with back annotated timing /

Narayanaswamy, Sathyanarayanan. January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 99-101). Also available via the Internet.
14

Hierarchical test generation for VHDL behavioral models /

Pan, Bi-Yu, January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 89-90). Also available via the Internet.
15

Mapping conceptual graphs to primitive VHDL processes /

Shrivastava, Vikram M., January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaf 66). Also available via the Internet.
16

Generation of VHDL from conceptual graphs of informal specifications /

Honcharik, Alexander J., January 1993 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaf 64). Also available via the Internet.
17

Suitability of the SRC-6E reconfigurable computing system for generating false radar image

Macklin, Kendrick R. 06 1900 (has links)
Approved for public release; distribution is unlimited / Communication is an essential skill for every military officer. Their jobs are accomplished through communication This thesis evaluates the usefulness of the SRC-6E reconfigurable computing system for a radar signal processing application and documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E. The research builds on previous work which implemented a false radar imaging algorithm on the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of SRC-6E solution. The results show that the SRC-6E provides and effective solution for implementations with greater than 64 range bins. An evaluation of the SRC-6E difficulty of use is conducted, including a discussion of required skills, experience and development times. The algorithm test code is included in the appendices.
18

Suitability of the SRC-6E reconfigurable computing system for generating false radar image /

Macklin, Kendrick R. January 2004 (has links) (PDF)
Thesis (M.S. in Computer Science)--Naval Postgraduate School, June 2004. / Thesis advisor(s): Neil Rowe. Includes bibliographical references (p. 129-130). Also available online.
19

Benchmarking and analysis of the SRC-6E reconfigurable computing system /

Macklin, Kendrick R. January 2003 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Douglas Fouts, Ted Lewis. Includes bibliographical references (p. 125). Also available online.
20

UML modeling for VHDL designs / Unified Modeling Language modeling for Very High Speed Integrated Circuit Hardware Description Language designs

Sprunger, Steven J. January 2008 (has links)
Unified Modeling Language (UML) allows software engineers to use a standard way of expressing a design approach at a high level. The benefits of system modeling are well accepted in the software development community. Modeling of Very High Speed Integrated Circuit Hardware Description Language (VHDL) designs, for synthesizing into hardware, is a common practice also. The research herein looks at system modeling of a design using UML, in which there are both software and hardware components. The idea is to explore modeling of the system with the ability to abstract whether the implementation of a particular function is realized in software or hardware. The designer can then model/evaluate a given system design approach and later allocate functions to software and hardware, as appropriate to meet constraints such as performance, cost, schedule. Since using UML for software is a standard approach, this research investigates the UML to hardware path via VHDL. / Department of Computer Science

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