Approved for public release, distribution is unlimited / This thesis outlines the development, programming, and testing a logical interface between a radar system, the AN/SPS-65(V)1, and a general-purpose reconfigurable computing platform, the SRC Computer, Inc. model, the SRC-6E. To confirm the proper operation of the interface and associated subcomponents, software was developed to perform basic radar signal processing. The interface, as proven by the signal processing results, accurately reflects radar imagery generated by the radar system when compared to maps of the surrounding area. The research accomplished here will allow follow on research to evaluate the potential benefits reconfigurable computing platforms offer for radar signal processing. / Captain, United States Marine Corps

Thesis (MScEng)--Stellenbosch University, 2005. / ENGLISH ABSTRACT: This thesis investigates the possible use of NAND flash memory for a mass memory unit on a micro-satellite. The investigation begins with an analysis of NAND flash memory devices including the complexity of the internal circuitry and the occurrence of bad memory sections (bad blocks). Design specifications are produced and various design architectures are discussed and evaluated. Subsequently, a four bus serial access architecture using 16- bit NAND flash devices was chosen to be developed further. A VHDL design was created in order to realise the intended system functionality. The main functions of the design include a sustained write data rate of 24 MB/s, bad block management, multiple image storing, error checking and correction, defective device handling and reading while writing. The design was simulated extensively using NAND flash simulation models. Finally, a demonstration test board was designed and produced. This board includes an FPGA and an array of 16 8-bit NAND flash devices. The board was tested sucessfully and a write data rate of 12 MB/s was achieved along with all the other main functions. / AFRIKAANSE OPSOMMING: Hierdie tesis ondersoek die moontlike gebruik van NAND flash tegnologie as die geheue eenheid van ’n mikrosatelliet. As ’n beginpunt word NAND flash tegnologie ondersoek in terme van die kompleksiteit van interne stroombane en die voorkoms van defektiewe geheuesegmente. Daarna word ontwerpspesifikasies voortgebring en verskillende ontwerpsmoontlikhede met mekaar vergelyk. Vanuit hierdie oorwegings is daar besluit om die oplossing te implementeer met ’n vier-bus seri¨ele struktuur bestaande uit 16-bis NAND flash toestelle. Om die ontwerpspesifikasies te realiseer, is ’n VHDL stelsel geskep. Die belangrikste funksies van hierdie stelsel is ’n konstante skryftempo van 24 MB/s, die bestuur van defektiewe geheuesegmente, die stoor van meer as een beeld, foutopsporing en -herstel, optimale werking in die geval van defektiewe geheuetoestelle en laastens, die gelyktydige lees en skryf van data. Die stelsel is breedvoerig getoets met NAND flash simulasiemodelle. Ten slotte is ’n fisiese demonstrasiebord, bestaande uit ’n FPGA en 16 8-bis NAND flash toestelle, ontwerp en gebou. Fisiese metings was ’n sukses. ’n Skryftempo van 12 MB/s is gehaal, tesame met die korrekte werking van die ander hooffunksies.

Made available in DSpace on 2014-06-11T19:22:31Z (GMT). No. of bitstreams: 0 Previous issue date: 2009-10-30Bitstream added on 2014-06-13T20:09:43Z : No. of bitstreams: 1 almeida_ts_me_ilha.pdf: 5032122 bytes, checksum: ba20bdd1ce902754e7b772b2be3cc785 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Neste trabalho, apresenta-se o desenvolvimento e a avaliação de duas ferramentas que auxiliam projetos de circuitos eletrônicos, sejam eles projetos de sistemas digitais ou de sistemas mistos (sinais digitais e sinais analógicos). A partir de um diagrama de transição de estados, modelado em ambiente Stateflow®, a primeira ferramenta, denominada SF2HDL, realiza a extração de linguagens de descrição de hardware, podendo ser VHDL ou Verilog HDL. Sendo ainda capaz de extrair uma tabela de transição de estados padronizada, que, posteriormente, foi utilizada como entrada pelo programa TABELA, o qual realiza a minimização do sistema digital. A máquina de estados finitos, alvo da tradução, pode ser descrita tanto pelo modelo de Mealy como pelo modelo de Moore. Como estudos de caso, foram utilizados quatro códigos de linhas empregados em sistemas de telecomunicações. A segunda ferramenta é um aperfeiçoamento de uma ferramenta já existente, denominada MS2SV, empregada na síntese de sistemas mistos. O MS2SV é capaz de gerar uma descrição em VHDL-AMS estrutural, a partir de um modelo descrito em alto nível de abstração no ambiente Simulink®. Toda a estrutura de projeto necessária para a simulação e análise do sistema no ambiente SystemVision™, também é gerado pelo MS2SV. Foram utilizados quatro modelos de conversor de dados do tipo DAC (Digital to Analog Conversor), para avaliar o desempenho da ferramenta. Nesse contexto, as duas ferramentas permitem maior flexibilidade ao projetista, traduzindo descrições em níveis de abstração diferentes, o que permite uma análise mais detalhada do funcionamento do sistema e facilitando a sua implementação física / In this work, it’s shown the development and evaluation of two tools to aid in electronic circuits projects, be them digital systems projects or for mixed systems (digital and analogical signs). From a states transition diagram modeled in Stateflow® environment, the first tool, named SF2HDL, performs the extraction of hardware description languages, which could be VHDL or Verilog HDL. It is also capable of extracting states transition table standardized, which later was used as a TABELA program, which accomplishes the minimization of the digital system. The target finite state machine of the translated can be described by the Mealy model as much as the Moore model. As case studies were used four code lines employed in telecommunications systems. The second tool is an improvement of an already existent tool, known as MS2SV, used in the synthesis of mixed systems. The MS2SV is able to generate a description in structural VHDL-AMS, from a model described in high level of abstraction in the Simulink® environment. The whole project structure necessary for the simulation and analysis of the system by the SystemVision™ environment is also generated by MS2SV. Four DAC (Digital to Analog Converter) were used to evaluate the tool is performance. In that context, both tools allow a greater flexibility to the planner, translating descriptions in different abstraction levels, which allows a more detailed analysis of the systems behavior and making its physical implementation easier

As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults. / Master of Science

In this thesis, several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the precomputed tests for the individual processes of the model from which it constructs a test sequence that exercises the model hierarchically. The construction of the test sequence is automatic if the tests for the individual processes of the model are provided. The test sequence derived can be used for the simulation of the model. By comparing the simulation outputs with the data sheet or the design specifications of the corresponding circuit, a user can tell if the functionality of the model is as expected or any functional faults exist. Simulation results and conclusions are given. Some suggestions for further improvements of the program are discussed. / Master of Science

This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral model. It generates a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL behavioral models with realistic timing and thus quickens the design cycle. / Master of Science

This thesis describes the development of the Process Test Generation (PTG) software for the testing of single-process VHDL behavioral models. The PTG software, along with Hierarchical Behavioral Test Generator (HBTG) and Modeler's Assistant, forms a part of the Automatic Test Generation System being developed at Virginia Tech. The PTG software transforms the VHDL description of a circuit, given by Modeler's Assistant, into a Control Flow Graph (CFG) that describes the control and data flow information in the behavioral model. The process test generation algorithm, called the PTG algorithm, uses the CFG to generate stimulus/response test sets that test all the functions of the VHDL model. The algorithm creates events on signals, propagates these events and uses simulation to obtain responses. Various features present in the software like the generation of the Control Flow Graph, the PTG algorithm, and the construction of paths through the CFG to propagate and justify events, are discussed. The test sets generated by PTG can be used for the hierarchical test generation by HBTG, which was developed earlier. Another program, called Test Bench Generator (TBG), is presented in this thesis. It is used to convert the test sequence generated by HBTG into a VHDL Test Bench that can be used for simulation. / Master of Science

Approved for public release, distribution is unlimited / This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDLTM. Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP s and a cascade of 16 RBP s were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP s together, representing the actual 512 RBP s. As a result of this research, the majority of the DIS was functionally tested and verified. / First Lieutenant, Turkish Army

A ferramenta ChipCflow vem sendo desenvolvida nos últimos quatro anos, inicialmente a partir de um projeto de arquitetura a fluxo de dados dinâmico em hardware reconfigurável, mas agora como uma ferramenta de compilação. Ela tem como objetivo a execução de algoritmos por meio do modelo de arquitetura a fluxo de dados associado ao conceito de dispositivos parcialmente reconfiguráveis. Sua característica principal é acelerar o tempo de execução de programas escritos em Linguagem de Programação de Alto Nível (LPAN), do inglês, High Level Languages, em particular nas partes mais intensas de processamento. Isso é feito por meio da implementação dessas partes de código diretamente em hardware reconfigurável - utilizando a tecnologia Field-programmable Gate Array (FPGA) - aproveitando ao máximo o paralelismo considerado natural do modelo a fluxo de dados e as características do hardware parcialmente reconfigurável. Neste trabalho, o objetivo é a prova de conceito do processo de partição e do protocolo de comunicação entre as partições definidas a partir de um Grafo de Fluxo de Dados (GFD), para a execução direta em hardware reconfigurável utilizando Reconfiguração Parcial Dinâmica (RPD). Foi necessário elaborar um mecanismo de partição e protocolo de comunicação entre essas partições, uma vez que a RPD insere características tecnológicas limitantes não encontradas em hardwares reconfiguráveis mais tradicionais. O mecanismo criado se mostrou parcialmente adequado à prova de conceito, significando a possibilidade de se executar GFDs na plataforma parcialmente reconfigurável. Todavia, os tempos de reconfiguração inviabilizaram a proposta inicial de se utilizar RPD para diminuir o tempo de tag matching dos GFDs dinâmicos / The ChipCflow tool has been developed over the last four years, initially from an architectural design the flow of Dynamic Data in reconfigurable hardware, but now as a compilation tool. It aims to run algorithms using the model of the data flow architecture associated with the concept of partially reconfigurable devices. Its main feature is to accelerate the execution time of programs written in High Level Languages, particularly in the most intense processing. This is done by implementing those parts of code directly in reconfigurable hardware - using FPGA technology - leveraging the natural parallelism of the data flow model and characteristics of the partially reconfigurable hardware. In this work, the main goal is the proof of concept of the partition process and protocol communication between the partitions defined from Data Flow Graph for direct execution in reconfigurable hardware using Active Partial Reconfiguration. This required a mechanism to partition and a protocol for communication between these partitions, since the Active Partial Reconfiguration inserts technological features limiting not found in traditional reconfigurable hardware. The mechanism developed is show to be partially adequate to the proof of concept, meaning the ability to run Data Flow Graphs in a platform that is partially reconfigurable. However, the reconfiguration time inserts a great overhead into the execution time, which made the proposal of the use of Active Partial Reconfiguration to decrease the time matching Data Flow Graph unfeasible

Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface topology, phase information can be calculated and a 3D model constructed. Phase Measuring Profilometry (PMP) is a particular type of SLI that requires three or more patterns temporarily multiplexed. High speed PMP attempts to scan moving objects whose motion is small so as to have little impact on the 3-D model. Given that practically all machine vision cameras and high speed cameras employ a Field Programmable Gate Array (FPGA) interface directly to the image sensors, the opportunity exists to do the processing on camera. This thesis focuses on the design, implementation, testing, and evaluation of a camera-projector system to implement a PMP dual-frequency scheme for 3-D shape measurement on a single FPGA chip. The processor architecture is implemented and tested using the Xilinx Spartan 3 FPGA chip on an Opal Kelly development board. The hardware is described using VHDL and Verilog Hardware Description Languages (HDLs).