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1	Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer Guthrie, Thomas G. 03 1900 (has links) Approved for public release, distribution is unlimited / This thesis outlines the development, programming, and testing a logical interface between a radar system, the AN/SPS-65(V)1, and a general-purpose reconfigurable computing platform, the SRC Computer, Inc. model, the SRC-6E. To confirm the proper operation of the interface and associated subcomponents, software was developed to perform basic radar signal processing. The interface, as proven by the signal processing results, accurately reflects radar imagery generated by the radar system when compared to maps of the surrounding area. The research accomplished here will allow follow on research to evaluate the potential benefits reconfigurable computing platforms offer for radar signal processing. / Captain, United States Marine Corps Radar transmitters Signal processing Computer hardware description languages C programming Field programmable logic device (FPLA) Hardware description language (HDL) Programmable logic device (PLD) Radar Reconfigurable computing Signal processing VHDL