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Test selection and fault simulation for analog integrated circuits /

Thesis (Ph. D.)--University of Washington, 2001. / Vita. Includes bibliographical references (leaves 94-97).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/48102814
Date January 2001
CreatorsDevarayanadurg, Giri V.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
TypeTheses
SourceConnect to this title online; UW restricted

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