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An FPGA architecture for improved arithmetic performance /

Thesis (M. Eng. Sc.)--University of Queensland, 2002. / Includes bibliographical references.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/52249883
Date January 2001
CreatorsRajagopalan, Kamal.
PublisherSt. Lucia, Qld.,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceFPGA architecture for improved arithmetic performance</a><br>Read the abstract of the thesis.

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