The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made packet-switched networks-on-chip (NoCs) a more compelling choice for the communication backbone in next-generation systems. NoC designs are sensitive to many design parameters—hence the study of new NoCs can be time-intensive. We propose DART, a fast and flexible FPGA-based NoC simulation architecture. Rather than laying the NoC out directly on the FPGA like previous approaches, DART virtualizes the NoC by mapping its components to a generic NoC simulation engine. This approach has two main advantages: (i) since it is virtualized it can simulate any NoC; and (ii) any NoC can be mapped to the engine without the time-consuming process of rebuilding the FPGA design. We demonstrate that an implementation of DART on a Virtex-II Pro FPGA achieves over 100x speedup over the cycle-based software simulator Booksim, while maintaining the same level of simulation accuracy.
| Identifer | oai:union.ndltd.org:TORONTO/oai:tspace.library.utoronto.ca:1807/25504 |
| Date | 30 December 2010 |
| Creators | Wang, Danyao |
| Contributors | Steffan, J. Gregory, Enright Jerger, Natalie |
| Source Sets | University of Toronto |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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