<p>In this master thesis, we design and implemented a super mode for multiple streaming signal processing applications, and got the timing budget based on Senior DSP processor. This work presented great opportunity to study the real-time system and firmware design knowledge on embedded system.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-10431 |
| Date | January 2007 |
| Creators | Han, Shuang |
| Publisher | Linköping University, Department of Electrical Engineering, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
Page generated in 0.0017 seconds