Through Silicon Vias (TSVs) are vertical interconnections providing the shortest possible signal paths between vertically stacked chips in 3D packaging. In this thesis, TSVs are fabricated and two novel approaches for the metal filling of TSVs are investigated. A wire bonder is utilized to apply TSV core material in the form of gold stud bumps. The metal filling approaches are carried out by 1) squeezing stud bumps down the TSV holes by utilizing a wafer bonder and 2) stacking stud bumps on the outer periphery of the TSV holes and thereby forcing the material further down. Both approaches have successfully filled TSV holes of varying depths and no voids have been observed. The squeezing approach reaches measured depths of up to 52.9 μm and the stacking approach reaches depths of up to 100 μm.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:kth-145552 |
| Date | January 2014 |
| Creators | Wennergren, Karl Fredrik |
| Publisher | KTH, Mikro- och nanosystemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | EES Examensarbete / Master Thesis |
Page generated in 0.2486 seconds