In this master thesis, we design and implemented a super mode for multiple streaming signal processing applications, and got the timing budget based on Senior DSP processor. This work presented great opportunity to study the real-time system and firmware design knowledge on embedded system.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-10431 |
| Date | January 2007 |
| Creators | Han, Shuang |
| Publisher | Linköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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