This paper presents a reconfigurable FFT architecture for variable length andmultistreaming WiMax wireless standard. The architecture processes 1 streamof 2048-pt FFT, up to 2 streams of 1024-pt FFT or up to 4 streams of 512-ptFFT. The architecture consists of 11 SDF pipelined stages and radix-2 butterflyis calculated in each stage. The sampling frequency of the system is varied inaccordance with FFT length. The wordlength and buffer length in each stage isconfigurable depending on the FFT length. Latch-free clock gating technique isused to reduce power consumption.The architecture is synthesized for Virtex-6 XCVLX760 FPGA. Experimentalresults show that the architecture achieves the throughput as required by theWiMax standard and the design has additional features compared to the previousapproaches. The design used 1% of the total available FPGA resources andmaximum clock frequency of 313.67 MHz was achieved.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-72983 |
| Date | January 2011 |
| Creators | Padma Prasad, Boopal |
| Publisher | Linköpings universitet, Elektroniksystem |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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