This paper presents a reconfigurable FFT architecture for variable length andmultistreaming WiMax wireless standard. The architecture processes 1 streamof 2048-pt FFT, up to 2 streams of 1024-pt FFT or up to 4 streams of 512-ptFFT. The architecture consists of 11 SDF pipelined stages and radix-2 butterflyis calculated in each stage. The sampling frequency of the system is varied inaccordance with FFT length. The wordlength and buffer length in each stage isconfigurable depending on the FFT length. Latch-free clock gating technique isused to reduce power consumption.The architecture is synthesized for Virtex-6 XCVLX760 FPGA. Experimentalresults show that the architecture achieves the throughput as required by theWiMax standard and the design has additional features compared to the previousapproaches. The design used 1% of the total available FPGA resources andmaximum clock frequency of 313.67 MHz was achieved.

In cryptographic processor design, the selection of functional primitives and connection structures between these primitives are extremely crucial to maximize throughput and flexibility. Hence, detailed analysis on the specifications and requirements of existing crypto-systems plays a crucial role in cryptographic processor design. This thesis provides the most comprehensive literature review that we are aware of on the widest range of existing cryptographic algorithms, their specifications, requirements, and hardware structures. In the light of this analysis, it also describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, that is designed to support both today's and tomorrow's encryption standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only crypto-specific processor targeting the future standards as well. Unlike previous work, we aim for maximum throughput for all known encryption standards, and to support future standards as well. Our 1GHz design achieves a peak throughput of 128Gbps for AES-128 which is competitive with ASIC designs and has 25X and 160X higher throughput per area than CPU and GPU solutions, respectively. / text

To compete, manufacturing companies need production systems that quickly can respond to changes. To handle change drivers such as volume variations or new product variants, reconfigurability is advocated as a competitive means. This implies an ability to add, remove, and/or rearrange the structure of the production system to be ready for future changes. Still, it is not clear how the production system design process can capture and support the de-sign of reconfigurable production systems. Therefore, the objective of this thesis is to increase the knowledge of how to support the design of reconfig-urable production systems. Reconfigurability could be defined by a number of reconfigurability char-acteristics including convertibility, scalability, automatibility, mobility, modularity, integrability, and diagnosability. In eight case studies, reconfigu-rability characteristics in production system design were studied in order to investigate reconfigurability needs, knowledge, and practice in manufactur-ing companies. In three of the case studies reconfigurable production sys-tems were studied to identify the links between change drivers and reconfig-urability characteristics. In the remaining five case studies, reconfigurability in the production system design processes was addressed in terms of needs, prerequisites, and consideration. Based on the literature review and the case studies, support for reconfigu-rable production system design is suggested including two parts. The first part comprises support for analyzing the need for reconfigurability. Based on relevant change drivers the need for reconfigurability must be identified to enable selection of right type and degree of reconfigurability for each specif-ic case of application. A comprehensive view of the reconfigurability charac-teristics is presented and links between change drivers and reconfigurability characteristics are described. The characteristics are divided into critical characteristics, that lead to a capacity or functionality change of the produc-tion system, and supporting characteristics, that reduce system reconfigura-tion time but do not necessarily lead to a modification of functionality or capacity of the production system. The second part provides support in how to consider reconfigurability in the production system design process. A holistic perspective is crucial to design reconfigurable production systems and therefore constituent parts of a production system are described. Accord-ing to their character physical, logical, and human reconfiguration must be considered through the whole production system design process.

Product and system designers face many challenges in the modern world. Designing products that will be subject to emerging or uncertain requirements can be one of the most significant of these challenges. A major risk associated with emerging or uncertain requirements is premature obsolescence. Large-scale, complex engineered systems, such as, aircraft, spacecraft, large seagoing vessels, communication and power systems are especially susceptible to this issue. However, this challenge is not limited to only large-scale complex systems. Even relatively simple products can suffer from premature obsolescence and even failure to be initially accepted, due to inadequately understood or changing requirements. One approach to mitigating this challenge is to increase the product's flexibility and adaptability, thus enabling it to evolve or adapt to meet unforeseen requirements. The flexibility of a product to adapt to new or changing requirements has been shown to increase acceptance rates and reduce the risk of premature obsolescence. Methodologies to accomplish this include product family platform design, transformable product design, reconfigurable product design and modular product design. The literature presents several techniques to aid designers, such as design structure matrices (DSM), change propagation analysis, change modes and effects analysis (CMEA), metrics and guides. These techniques address the challenge by seeking to understand and manage the relationships and interfaces between functions or components within the design. While these are excellent techniques, they do not provide quantifiable functions or models for the design alternatives. Quantifiable functions and models are of value to designers, because they enable numerical design aids. Numerical optimization techniques have been shown to aid designers in efficiently determining appropriate design parameters. This dissertation identifies, analyzes and presents new techniques, which are based on designed-in excess capabilities and to which numerical optimization can be directly applied. There are four parts to the dissertation. In the first part, a technique is presented for determining the relative value of a product, which has been over-designed (excess capabilities) to address future requirements versus redesigning the product once the future requirements emerge. It is shown that in many cases the over-design approach provides greater benefit. In the second part, a numerical metric for the evolvability of a product based on excess capability is presented. An important result of this metric is that the evolvability of a product and the usability of each excess capability can be numerically determined. The third part presents a technique to design products for increased adaptability, based on optimally designed-in excess. Deterministic, and non-deterministic conditions are included in this optimization. Once a numerical model of the design is available the issue of uncertain requirements can be mitigated by directly focusing on the uncertainties. In the fourth part, a technique employing optimization and sensitivity analysis is used to systematically and efficiently guide the designer toward minimizing or eliminating the most critical uncertainties.

<p>Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis.</p><p>Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware.</p><p>In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on.</p><p>One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.</p>

Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis. Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware. In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on. One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.

As limitações resultantes do avanço das tecnologias de integração, como o crescente aumento da densidade de potência, levando à necessidade de redução da frequência de operação dos circuitos somados à necessidade de redução do consumo energético, sejam por motivos ecológicos ou para melhor suprir dispositivos portáteis, trazem a necessidade de maior intervenção e personalização do hardware em relação às exigências do software. Em diversos níveis estas intervenções podem ser aplicadas, onde a granularidade pode variar desde elementos de processamento sendo completamente desativados até processadores tendo apenas unidades funcionais sendo desativadas, memórias cache reconfiguradas em tamanho e associatividade, etc. Entretanto, a reconfiguração do hardware deve atingir todas as etapas destes sistemas para que seja possível atingir redução satisfatória em termos de potência e consumo de energia. Além da integração acelerada de elementos de processamento em um mesmo circuito integrado, a crescente concentração de heterogêneas tarefas em um mesmo dispositivo, leva à integração de elementos de processamento também heterogêneos, e por consequência diferentes comportamentos variando de acordo com a aplicação. Para justificar esta reconfigurabilidade e heterogeneidade dos elementos de processamento este trabalho apresenta um estudo que possibilita a observação da execução de diferentes aplicações em elementos de processamento amplamente reconfiguráveis. Para que a reconfigurabilidade e heterogeneidade possam ser aplicáveis, foi inserida uma ferramenta capaz de manter a compatibilidade entre o elemento de processamento mestre e os elementos de processamento aceleradores reconfiguráveis disponíveis. Os experimentos apresentados baseiam-se na necessidade de manter a menor quantidade de silício ativa, acelerando o código fonte enquanto reduz-se o consumo de energia. Somada a redução de energia, a compatibilidade binária é levada em consideração buscando a manutenção da produtividade quando da utilização de sistemas heterogêneos reconfiguráveis. / The limitations resulting from the advancement of integration technologies, such as the increasing power density, leading to the need to reduce the operating frequency of the circuits added to the need to reduce energy consumption, whether for environmental reasons or to better serve mobile devices, bring the need for greater intervention and hardware customization to the demands of the software. To varying degrees these interventions can be applied where the granularity can range from processing elements being completely disabled until processors having only functional units being disabled, reset cache memories in size and associativity, etc. However, the reconfiguration of hardware should reach all stages of these systems so that you can achieve satisfactory reduction in power and energy consumption. In addition to the accelerated integration of processing elements on a single integrated circuit, the increasing concentration of heterogeneous tasks in a same device, also leads to the integration of heterogeneous processing elements, and therefore different behavior varies according to the application. To justify this reconfigurability and variety of processing elements this work presents a study that allows the observation of the implementation of different applications in widely reconfigurable processing elements. For reconfigurability and heterogeneity may be applicable, a tool to maintain compatibility between the master processing element and accelerators reconfigurable processing elements available was inserted. The experiments presented are based on the need to maintain the lowest amount of active silicon, accelerating the source code while reducing power consumption. Added to energy reduction, binary compatibility is taken into consideration seeking to maintain productivity when using reconfigurable heterogeneous systems.

As limitações resultantes do avanço das tecnologias de integração, como o crescente aumento da densidade de potência, levando à necessidade de redução da frequência de operação dos circuitos somados à necessidade de redução do consumo energético, sejam por motivos ecológicos ou para melhor suprir dispositivos portáteis, trazem a necessidade de maior intervenção e personalização do hardware em relação às exigências do software. Em diversos níveis estas intervenções podem ser aplicadas, onde a granularidade pode variar desde elementos de processamento sendo completamente desativados até processadores tendo apenas unidades funcionais sendo desativadas, memórias cache reconfiguradas em tamanho e associatividade, etc. Entretanto, a reconfiguração do hardware deve atingir todas as etapas destes sistemas para que seja possível atingir redução satisfatória em termos de potência e consumo de energia. Além da integração acelerada de elementos de processamento em um mesmo circuito integrado, a crescente concentração de heterogêneas tarefas em um mesmo dispositivo, leva à integração de elementos de processamento também heterogêneos, e por consequência diferentes comportamentos variando de acordo com a aplicação. Para justificar esta reconfigurabilidade e heterogeneidade dos elementos de processamento este trabalho apresenta um estudo que possibilita a observação da execução de diferentes aplicações em elementos de processamento amplamente reconfiguráveis. Para que a reconfigurabilidade e heterogeneidade possam ser aplicáveis, foi inserida uma ferramenta capaz de manter a compatibilidade entre o elemento de processamento mestre e os elementos de processamento aceleradores reconfiguráveis disponíveis. Os experimentos apresentados baseiam-se na necessidade de manter a menor quantidade de silício ativa, acelerando o código fonte enquanto reduz-se o consumo de energia. Somada a redução de energia, a compatibilidade binária é levada em consideração buscando a manutenção da produtividade quando da utilização de sistemas heterogêneos reconfiguráveis. / The limitations resulting from the advancement of integration technologies, such as the increasing power density, leading to the need to reduce the operating frequency of the circuits added to the need to reduce energy consumption, whether for environmental reasons or to better serve mobile devices, bring the need for greater intervention and hardware customization to the demands of the software. To varying degrees these interventions can be applied where the granularity can range from processing elements being completely disabled until processors having only functional units being disabled, reset cache memories in size and associativity, etc. However, the reconfiguration of hardware should reach all stages of these systems so that you can achieve satisfactory reduction in power and energy consumption. In addition to the accelerated integration of processing elements on a single integrated circuit, the increasing concentration of heterogeneous tasks in a same device, also leads to the integration of heterogeneous processing elements, and therefore different behavior varies according to the application. To justify this reconfigurability and variety of processing elements this work presents a study that allows the observation of the implementation of different applications in widely reconfigurable processing elements. For reconfigurability and heterogeneity may be applicable, a tool to maintain compatibility between the master processing element and accelerators reconfigurable processing elements available was inserted. The experiments presented are based on the need to maintain the lowest amount of active silicon, accelerating the source code while reducing power consumption. Added to energy reduction, binary compatibility is taken into consideration seeking to maintain productivity when using reconfigurable heterogeneous systems.

As limitações resultantes do avanço das tecnologias de integração, como o crescente aumento da densidade de potência, levando à necessidade de redução da frequência de operação dos circuitos somados à necessidade de redução do consumo energético, sejam por motivos ecológicos ou para melhor suprir dispositivos portáteis, trazem a necessidade de maior intervenção e personalização do hardware em relação às exigências do software. Em diversos níveis estas intervenções podem ser aplicadas, onde a granularidade pode variar desde elementos de processamento sendo completamente desativados até processadores tendo apenas unidades funcionais sendo desativadas, memórias cache reconfiguradas em tamanho e associatividade, etc. Entretanto, a reconfiguração do hardware deve atingir todas as etapas destes sistemas para que seja possível atingir redução satisfatória em termos de potência e consumo de energia. Além da integração acelerada de elementos de processamento em um mesmo circuito integrado, a crescente concentração de heterogêneas tarefas em um mesmo dispositivo, leva à integração de elementos de processamento também heterogêneos, e por consequência diferentes comportamentos variando de acordo com a aplicação. Para justificar esta reconfigurabilidade e heterogeneidade dos elementos de processamento este trabalho apresenta um estudo que possibilita a observação da execução de diferentes aplicações em elementos de processamento amplamente reconfiguráveis. Para que a reconfigurabilidade e heterogeneidade possam ser aplicáveis, foi inserida uma ferramenta capaz de manter a compatibilidade entre o elemento de processamento mestre e os elementos de processamento aceleradores reconfiguráveis disponíveis. Os experimentos apresentados baseiam-se na necessidade de manter a menor quantidade de silício ativa, acelerando o código fonte enquanto reduz-se o consumo de energia. Somada a redução de energia, a compatibilidade binária é levada em consideração buscando a manutenção da produtividade quando da utilização de sistemas heterogêneos reconfiguráveis. / The limitations resulting from the advancement of integration technologies, such as the increasing power density, leading to the need to reduce the operating frequency of the circuits added to the need to reduce energy consumption, whether for environmental reasons or to better serve mobile devices, bring the need for greater intervention and hardware customization to the demands of the software. To varying degrees these interventions can be applied where the granularity can range from processing elements being completely disabled until processors having only functional units being disabled, reset cache memories in size and associativity, etc. However, the reconfiguration of hardware should reach all stages of these systems so that you can achieve satisfactory reduction in power and energy consumption. In addition to the accelerated integration of processing elements on a single integrated circuit, the increasing concentration of heterogeneous tasks in a same device, also leads to the integration of heterogeneous processing elements, and therefore different behavior varies according to the application. To justify this reconfigurability and variety of processing elements this work presents a study that allows the observation of the implementation of different applications in widely reconfigurable processing elements. For reconfigurability and heterogeneity may be applicable, a tool to maintain compatibility between the master processing element and accelerators reconfigurable processing elements available was inserted. The experiments presented are based on the need to maintain the lowest amount of active silicon, accelerating the source code while reducing power consumption. Added to energy reduction, binary compatibility is taken into consideration seeking to maintain productivity when using reconfigurable heterogeneous systems.

An important factor in system longevity is service-phase evolvability, which is defined as the ability of a system to physically transform from one configuration to a more desirable configuration while in service. These transformations may or may not be known during the design process, and may or may not be reversible. A study of 210 engineered systems was performed and found that system excess and modularity allow a system to evolve while in service. Building on these observations, this thesis introduces mathematical relationships that map a system's excess and modularity to that system's ability to evolve. These relationships are derived from elastic potential energy theories. The use of the evolvability measure, and other related measures presented herein, are illustrated with simple numerical examples and applied to the design of US Navy nuclear aircraft carriers. Using these relationships, it is shown that the Navy's new Ford-class aircraft carrier is the most evolvable carrier designed to date. Though the evolvability relationships introduced here are generically derived based on excess and modularity, the aircraft carrier example presented considers only the system excess.