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Improving energy efficiency of reliable massively-parallel architectures

While transistor size continues to shrink every technology generation
increasing the amount of transistors on a die, the reduction in energy
consumption is less significant. Furthermore, newer technologies induce
fabrication challenges resulting in uncertainties in transistor and wire properties.
Therefore to ensure correctness, design margins are introduced resulting in
significantly sub-optimal energy efficiency. While increasing parallelism and the
use of gating methods contribute to energy consumption reduction, ultimately,
more radical changes to the architecture and better integration of architectural
and circuit techniques will be necessary. This dissertation explores one such
approach, combining a highly-efficient massively-parallel processor architecture
with a design methodology that reduces energy by trimming design margins.

Using a massively-parallel GPU-like (graphics processing unit) base-
line architecture, we discuss the different components of process variation and
design microarchitectural approaches supporting efficient margins reduction.
We evaluate our design using a cycle-based GPU simulator, describe the
conditions where efficiency improvements can be obtained, and explore the benefits
of decoupling across a wide range of parameters. We architect a test-chip that
was fabricated and show these mechanisms to work.

We also discuss why previously developed related approaches fall short
when process variation is very large, such as in low-voltage operation or as
expected for future VLSI technology. We therefore develop and evaluate a
new approach specifically for high-variation scenarios.

To summarize, in this work, we address the emerging challenges of
modern massively parallel architectures including energy efficient, reliable
operation and high process variation. We believe that the results of this work
are essential for breaking through the energy wall, continuing to improve the
efficiency of future generations of the massively parallel architectures. / text

Identiferoai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/ETD-UT-2012-05-5473
Date12 July 2012
CreatorsKrimer, Evgeni
Source SetsUniversity of Texas
LanguageEnglish
Detected LanguageEnglish
Typethesis
Formatapplication/pdf

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