The basic Power Electronics Building Block (PEBB) configurations are identified and conceptual PEBB modules are constructed and tested. Using the INCA (Inductance Calculator) parasitic extraction and the Saber circuit simulation software, the microscopic relationships between the parasitics of the packaging layout and their circuit electrical effects are cross-examined. The PEBB module with advanced packaging techniques is characterized in comparison with the wire-bond module. The soft-switching techniques are evaluated for PEBB applications. The Zero-Current-Transition (ZCT) is proved better because the parasitics in the power current flow path are absorbed into the resonant soft-switching operation. This makes the PEBBs insensitive to system integration.
Based on the building block concept, the discrete and large signal average models are developed for simulation, design, and analysis of large-scale PEBB-based systems. New average models are developed for half-bridge PEBB module and Space Vector Modulation (SVM). These models keep the exact information of the discontinuous SVM and the common mode component of the three-phase system. They can be used to construct the computer models of a power electronics system the same as the modularized hardware and perform time domain simulations with very fast speed. Further more, even though the system is modeled based on modularized concept on the ABC coordinates, it can be used to perform small signal analysis on the DQ coordinates as well.
Based on the developed models, the system-level interactions in integrated systems are investigated. Three interaction scenarios are presented: (1) the zero-sequence circulation current in paralleled three-phase rectifiers caused by the interleaved discontinuous SVM, (2) the load and source interactions caused by unbalanced load and small signal impedance overlap, and (3) the combined common mode noise caused by both front-end PWM rectifiers and load inverters. The interaction phenomena and mitigation methods are demonstrated through hardware testbed system.
The concept of dc bus conditioning is proposed. The bus conditioner is a bi-directional dc/dc converter programmed as a current controlled current source, which shunts the large signal ac current, which otherwise goes to the dc bus, into an isolated energy storage component. In addition to alleviate the source and load interactions, it increases the load impedance/decreases the bus impedance and provides more stability margins to the distribution system. The dc bus conditioner concept and its functions are demonstrated through system simulation and preliminary hardware experiment. / Ph. D.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/28123 |
| Date | 09 July 1999 |
| Creators | Xing, Kun |
| Contributors | Electrical and Computer Engineering, Lee, Fred C., Sable, Don M., Nelson, Douglas J., Chen, Dan Y., Borojević, Dušan |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Dissertation |
| Format | application/pdf, application/pdf, application/pdf, application/pdf, application/pdf, application/pdf, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | ch2.pdf, ch6.pdf, ch5.pdf, ch4.pdf, ch3.pdf, ch1.pdf, ch0.pdf, ch7.pdf |
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