An integrated circuit processing schedule is presented that enables fabrication of both high speed I²L gates and high voltage linear type transistors on the same silicon starting substrate material. This process design circumvents conflicting processing requirements normally encountered in considering an I²L/Linear compatible structure by providing two separate epitaxial thicknesses for the I²L and linear section of the chip. The electrical characteristics of the I²L cells and the linear transistors are presented to illustrate their dependence on the doping conditions and are shown to be in contrast to each other. As a consequence of the separate epitaxial thicknesses, independence of the processing constraints is achieved. Experimental results of linear transistors and I²L devices fabricated using this processing schedule are presented and compared to calculated and computer simulations. Modifications to the basic process design is shown possible and enhanced performance of I²L devices results.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/282891 |
| Date | January 1980 |
| Creators | Lalumia, Thomas Mariano |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Dissertation-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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